Role OverviewYou will own the front end automation that carries our silicon from RTL entry to a clean
handoff into DFT and implementation. The scope covers RTL design flows, verification
flows from simulation through prototyping, and the AI assisted tooling built over them.
Success is measured two ways. Front end engineers get more done, and the tools they
rely on stay up through every phase of the design cycle.
Responsibilities- Own the RTL design flows including build, lint, CDC and formal checks.
- Own register generation and the generator driven flows behind interfaces and integration.
- Own the DV flows including testbench build, regression execution and coverage collection.
- Own emulation and FPGA prototyping build and bring up.
- Build and deploy AI assisted tooling across design and verification workflows, working with CAD and Engineering Infrastructure on compute and model access.
- Keep these flows available through the design cycle, managing tool versions and turning around bug, upgrade and maintenance requests quickly.
- Measure and improve design and verification productivity, and move proven workflows into standard practice.
- Partner with DFT and physical design on handoff readiness, owning the DFT side flows that sit in the front end.
Required Qualifications- 8 or more years in design verification, design or CAD engineering, including ownership of a flow area.
- Strong SystemVerilog and RTL fluency with the ability to read and debug design and testbench code.
- Hands on experience building and running simulation and regression flows including testbench compile, coverage collection and results triage.
- Excellent Python skills and a track record of building tools that other engineers maintain.
- Working knowledge of front end design and verification EDA tools from Synopsys, Cadence or Siemens EDA.
- Working knowledge of Linux administration, distributed compute such as LSF or Slurm, and the storage and scaling constraints behind large regression workloads.
- Familiarity with databases and dashboarding tools such as Grafana for tracking flow health and regression metrics.
- Track record of supporting a live engineering flow with responsive issue turnaround, and the communication skills to work closely with design and verification engineers.
Preferred Qualifications- Experience with UVM, cocotb or Python based verification environments.
- Hands on experience applying LLMs or agentic systems to engineering workflows.
- Experience taking an SoC from RTL bring up through tapeout.
- Experience with emulation and FPGA prototyping platforms such as Palladium, Protium, Veloce or HAPS.
- Experience with retrieval augmented generation, fine tuning or evaluation frameworks for code models.
- Experience at an early stage semiconductor company.
$200,000 - $300,000 a year
Compensation & BenefitsAt Velaura, we believe exceptional talent deserves exceptional rewards. Compensation for this role includes a base salary and very competitive equity compensation, allowing team members to share in the company's long-term success.
The base pay listed represents a good faith estimate that the Company reasonably expects to pay for this position at the time of hire. Actual compensation will depend on multiple factors, including the candidate's skills, qualifications, relevant experience, and geographic location.
In addition to base salary and equity compensation, Velaura offers a comprehensive benefits package that may include medical, dental, and vision coverage; paid time off; flexible work arrangements; professional development opportunities; and other benefits designed to support the well-being and growth of our team.
Velaura is committed to pay equity and transparency and regularly benchmarks compensation to ensure we remain competitive in the market.
