Accelerator Compiler and Tool Chain Lead

Velaura

$200K — $500K *
Information Technology
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • Deep experience with compiler development and ML graph compilers.
  • Strong understanding of ML model formats and runtime/compiler interfaces.
  • Proficient in C++ and Python with experience in production-quality software.
  • Familiar with compiler frameworks like MLIR, LLVM, and TensorRT.
  • Strong grasp of correctness risks in compiler optimizations and graph rewrites.
  • Experience in collaborating with hardware architecture and firmware teams.
  • Proven leadership in technical teams or projects.

Responsibilities

  • Lead design and development of the AI accelerator compiler.
  • Oversee model ingestion and graph lowering from AI frameworks.
  • Define strategies for operator coverage, lowering rules, and graph transformations.
  • Develop optimization passes for tensor layout and hardware-specific scheduling.
  • Collaborate with runtime and driver teams for executable artifact requirements.
  • Partner with hardware teams on data movement and performance features.
  • Integrate quantization into the compiler, managing metadata and tradeoffs.
  • Build diagnostics to assist customers with performance bottlenecks and unsupported operators.

Benefits

  • Comprehensive medical, dental, and vision coverage.
  • Paid time off and flexible work arrangements.
  • Professional development opportunities.
  • Employee equity participation in the company's success.
Full Job Description
Role Overview

We are looking for an Accelerator Compiler Lead to own the compiler and model-lowering stack for Velaura's AI accelerator.This role will lead the path from customer AI models to optimized executable artifacts for our NPU, including graph import, operator lowering, compiler IR, graph transformations, quantization integration, code generation, graph partitioning, and compiler diagnostics. The ideal candidate has built or shipped compiler infrastructure for ML accelerators, GPUs, DSPs, or other heterogeneous compute targets.

Responsibilities
• Lead architecture and development of the AI accelerator compiler stack.
• Own model ingestion and graph lowering from frameworks and exchange formats such as PyTorch export flows, ONNX, TensorFlow Lite, or similar.
• Define operator coverage strategy, lowering rules, graph transformations, fusion, partitioning, and fallback behavior.
• Develop compiler optimization passes for tensor layout, tiling, memory movement, mixed precision, operator fusion, and hardware-specific scheduling.
• Work closely with accelerator runtime and driver teams to define executable artifact formats, metadata, memory planning requirements, profiling hooks, and runtime constraints.
• Partner with hardware architecture and NPU firmware teams on ISA, command streams, tensor layouts, data movement, hardware constraints, and compiler-visible performance features.
• Own quantization compiler integration, including calibration metadata, precision selection, scale handling, layout constraints, and accuracy/performance tradeoffs.
• Build compiler diagnostics that help customers understand unsupported operators, shape constraints, graph rewrites, quantization issues, and performance bottlenecks.
• Establish compiler verification and regression strategy for graph transformations,IR lowering, numerical behavior, model accuracy, and performance.
• Hire, mentor, and lead a team of compiler and ML systems engineers.

Required Qualifications
• Deep experience with compiler development, ML graph compilers, or code generation for accelerators, GPUs, DSPs, or heterogeneous compute systems.
• Strong understanding of ML model formats, graph IRs, operator lowering, tensor layouts, quantization, and runtime/compiler interfaces.
• Strong C++ and Python programming skills and experience building production-quality compiler or systems software.
• Experience with compiler frameworks or technologies such as MLIR, LLVM, TVM, XLA, IREE, Glow, TensorRT-like systems, OpenVINO-like systems, or equivalent.
• Strong understanding of correctness risks in compiler optimizations, graph rewrites, mixed precision, operator fusion, and hardware-specific lowering.
• Ability to work closely with hardware architects, firmware engineers, runtime engineers, model-integration teams, and SQA.
• Experience leading technical teams or major architecture areas.

Preferred Qualifications
• Experience with NPU, GPU, DSP, or AI accelerator compiler stacks.
• Experience with quantization-aware compilation, mixed precision, sparsity, pruning, graph partitioning, or hardware-specific scheduling.
• Experience supporting ONNX, PyTorch export, TensorFlow Lite, JAX/XLA,TorchDynamo/TorchInductor, or other model import flows.
• Familiarity with robotics, computer vision, CNNs, transformers, detection, segmentation, depth, SLAM-adjacent perception, or edge AI workloads.
• Experience building customer-facing compiler diagnostics and model-porting tools.
• Experience with model-zoo release processes, accuracy validation, and reproducible benchmark artifacts.
• Open-source compiler contributions or experience working with external framework communities.

$200,000 - $500,000 a year

Compensation & Benefits

At Velaura, we believe exceptional talent deserves exceptional rewards. Compensation for this role includes a competitive base salary, performance-based incentives, and equity participation, allowing team members to share in the company's long-term success.

Your base pay will depend on your skills, qualifications, experience, and location.

In addition to compensation, Velaura offers a comprehensive benefits package that may include medical, dental, and vision coverage; paid time off; flexible work arrangements; professional development opportunities; and other benefits designed to support the well-being and growth of our team.

Velaura is committed to pay equity and transparency and regularly benchmarks compensation to ensure we remain competitive in the market.

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