Job Description:

We are seeking a Principal Design Engineer, passionate individual with technical leadership capabilities to build complex system designs for Configuration, Security, Processor, Memory and High-Speed interfaces based on application requirements. The individual should be able to translate system requirements and architectural specifications into micro-architecture and implementation. The individual should have the ability to provide technical insights for engineering teams, provide continuous improvement in IP performance and ease-of-use in system integration.

Job Requirements:

• 20yrs experience of hardware IP and integration design
• Led a team of cross-functional engineers across multiple sites/geos
• Led multiple programs from concept to Tape Out and production release
• Expertise in System Verilog, Synthesis, and Static Timing Analysis
• Good understanding of DFx (test and debug) methodology on IP and chip level
• Ability to debug complex issues with floor-planning, power distribution network, system level clocking, timing closure and SIPI
• Deep experience in one or more of following domains: High speed interfaces (LPDDR5, USB4.0, Chip-to-Chip interconnects), System Interconnects (Coherent NoC, AMBA), processors (ARM, MIPS, RISC-V) and FPGA systems
• Experience debugging complex system level use cases through verification, emulation and system validation
• Programming skills (e.g.: C/C++, Perl, TCL or Python) and proficient in using GenAI and agentic AI methodologies for scaling design
• Strong written and oral communication skills. Frequent presentations to executive leadership on status of projects and roadmaps
• Ability to drive IP roadmap with deep engagement with leading IP vendors and execute competitive analysis and benchmarking
• The ability to stay on top of latest advancements in technology, design and AI

Qualifications:

• BS/MS/PhD in Electronics or Computer Engineering minimum of 20 years of FPGA/SoC design experience.
• Independent and self-motivated, capable of executing under dynamic environment and uncertainties

Pay & Benefits

Consistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location. Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience.

For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location. The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.

Base Pay Range
248400

In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.