Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, or related field.
• Minimum two years of relevant experience in digital design or verification.
• Proficient in writing specifications for IP or SoC verification processes.
• Experience with digital debugging tools for functional verification and test planning.
• Familiar with UVM for developing verification environments.
• Skilled in creating SVA/System Verilog assertions for protocol checking.
• Knowledgeable in AMBA protocol environments.
• Ability to leverage AI and ML technologies in the verification process.

Responsibilities

• Research, design, and test electronic components and systems for EDA and semiconductor IP.
• Develop DDR Memory Controller and Phy IP solutions for the development team.
• Perform functional verification of the DDR Memory Controller and Phy IP.
• Enhance the existing verification environment with new features.
• Ensure customer configuration cleanliness during verification regressions.
• Support customers with issues in the verification environment, functional and code coverage checks.
• Maintain design compliance with team-specific technical and quality requirements.

Benefits

• Telecommuting options available.
• Engagement with cutting-edge EDA and semiconductor technology.
• Opportunities for professional development within a collaborative team environment.