Advanced Micro Devices, Inc

Sr. Timing Methodology Engineer

Advanced Micro Devices, Inc$130K — $180K *
Consumer Technology
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • 5-7 years in custom or physical design and sign-off engineering
  • Proficient in using industry-standard physical design and sign-off tools
  • Experience with FPGA implementation tools
  • Demonstrated experience advocating for technical solutions
  • Excellent communication and collaboration skills
  • Solid programming skills in Python, Perl, and Tcl
  • Bachelor's or Master's degree in Computer Engineering or Electrical Engineering

Responsibilities

  • Define and develop design, timing, and power methodologies for advanced process nodes
  • Collaborate with implementation and sign-off teams to streamline processes
  • Work with CAD, power integrity, foundry teams, and EDA vendors to address sign-off risks
  • Foster cross-group collaboration to convert product planning requirements into methodologies

Benefits

  • Full access to AMD benefits package
  • Opportunities for continuous learning and professional development
  • Flexible work arrangements available
  • Support for employee wellness and work-life balance
Full Job Description
THE ROLE:

In this senior position, you will be defining, developing, and driving timing methodologies across the Adaptive and Embedded Computing Group. You will work closely with architecture, product planning, process, design, and product engineering teams to realize silicon solutions with best-in-class PPA. You will bring your experience and expertise to solve the teams most pressing challenges in sign-off and modeling methodologies at 2nm and beyond on monolithic and 2.5/3DIC adaptive SOCs and FPGAs. Your solutions will enable products to compete in markets from the edge to the cloud while pushing the limits of performance and efficiency.

THE PERSON:

You are detailed oriented, possessing effective communication skills, and an experienced problem solver. You are passionate about optimizing for power, performance and area while meeting schedules and managing cost. You embrace cross-functional collaboration and continuous learning. You are comfortable in converting high level requirements from product planning, foundry, and other stakeholders into a set of methodologies and guidelines for the design community.

KEY RESPONSIBILITIES:
  • Define, develop, optimize and drive design, timing and power methodologies for advance process nodes.
  • Collaborate with implementation and sign-off teams.
  • Collaborate with CAD, power integrity, foundry teams and EDA vendors to understand margins and sign-off risks and develop mitigation strategies.


PREFERRED EXPERIENCE:
  • Experienced custom, physical design and/or sign-off engineer
  • Expert user of industry-standard physical design, analysis, and sign-off tools
  • Experience with FPGA implementation tools.
  • Experience advocating for technical solutions in a collaborative team environment.
  • Excellent communication and collaboration skills
  • Good programming skills (Python, Perl, Tcl)


ACADEMIC CREDENTIALS:
  • Bachelors or Masters degree in computer engineering/Electrical Engineering


LOCATION:

San Jose, CA

This role is not eligible for visa sponsorship.

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Benefits offered are described: AMD benefits at a glance.

About Advanced Micro Devices, Inc

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Learn more about Advanced Micro Devices, Inc
Size
15,500 employees
Market Cap
$100.9 billion
Industry
Net Income
$2.4 billion
Founded
1969
5 Year Trend
+30.9%
Revenue
$9.7 billion
NASDAQ

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