Renesas is seeking a Senior Digital Design Verification Engineer to join our team developing complex power management SoCs. These products integrate digital control, telemetry, fault management, communication interfaces, configurable peripherals, and advanced power-control functions for AI, datacenter, enterprise computing, networking, and high-performance power delivery applications. You will independently own verification of significant blocks and features from planning through closure. The role combines hands-on UVM development, coverage-driven verification, complex debug, and close collaboration with architecture, RTL design, firmware, analog, validation, and systems teams. Responsibilities • Own verification of complex digital blocks or major SoC features from requirements analysis through coverage closure. • Develop feature-based verification plans from product, architecture, and microarchitecture specifications; identify gaps, ambiguities, corner cases, and risks. • Build and extend reusable SystemVerilog/UVM environments, including sequences, monitors, scoreboards, checkers, assertions, and coverage models. • Develop constrained random and targeted tests for normal operation, error handling, recovery, and system-level interactions. • Drive functional, code, toggle, FSM, and assertion coverage closure using regression and coverage data. • Debug RTL, testbench, assertion, integration, and regression failures; collaborate with design and firmware teams to isolate issues and verify fixes. • Automate regression, triage, reporting, and analysis workflows using scripting and modern engineering tools. • Communicate status, risks, dependencies, and closure evidence clearly; provide technical guidance to less-experienced engineers. Qualifications • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. • 4 or more years of relevant digital design verification experience, or equivalent directly applicable experience. • Demonstrated ownership of a complex block, subsystem, or major feature from verification planning through closure. • Strong proficiency in SystemVerilog, UVM, constrained random verification, functional coverage, and SystemVerilog Assertions. • Experience translating specifications into test plans, test scenarios, checkers, scoreboards, assertions, coverage models, and closure criteria. • Hands-on experience developing and debugging reusable UVM environments and analyzing complex regression failures. • Strong RTL and testbench debug skills, with the ability to distinguish design, environment, test, firmware, and specification issues. • Working knowledge of digital design fundamentals, including state machines, clocks and resets, interrupts, register interfaces, memories, and clock-domain crossings. • Proficiency in Linux and at least one scripting language such as Python, Bash, Perl, or Tcl. • Ability to work independently and collaborate effectively across architecture, design, firmware, analog, validation, and systems teams. Preferred Qualifications • Experience verifying complex SoCs, power management ICs, voltage regulators, digital controllers, or mixed-signal products. • Experience verifying RTL interfaces to embedded processors, memory-mapped peripherals, and firmware-controlled hardware features. • Familiarity with PMBus, AVSBus, SVID or SVI3, I2C, SPI, or similar control and communication protocols. • Understanding of telemetry, fault and alert handling, power sequencing, multiphase regulation, or digital control loops. • Experience with Cadence Xcelium, SimVision, vManager, JasperGold, Synopsys VCS, Verdi, or comparable tools. • Experience with formal verification, gate-level simulation, silicon bring-up, or pre-silicon-to-silicon correlation. • Experience improving regression infrastructure, coverage analytics, failure triage, or verification automation. What You Bring • Strong technical ownership and a disciplined approach to verification completeness. • Ability to reason beyond directed requirements and identify meaningful corner cases and feature interactions. • Clear communication of technical risk, progress, and signoff evidence. • A collaborative mindset and interest in improving verification methodology and productivity. Videos To Watch https://www.youtube.com/embed/k-zs4tB6nNc