Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of technical experience in physical design disciplines involving power delivery and advanced process technology nodes.
• Experience with power grid integrity (electromigration and IR drop) from budgeting to analysis to verification and signoff.
• Experience with place and route tools, electromigration and IR drop tools, and design rule check tools.

Preferred qualifications:

• Master's degree or PhD in electrical engineering, computer engineering, or computer science, with an emphasis on computer architecture.
• Experience owning power grid design working with physical design or implementation and architecture owners.
• Experience establishing voltage budgets and drop mitigation for new projects working with a power delivery network team.
• Experience with through-silicon via planning and 3D stack designs.
• Familiarity with low power design techniques (e.g., unified power format, dynamic voltage frequency scaling).

About the job

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will collaborate with physical design, circuits, technology, and package leads to overcome the slowing of Moore's law in advanced technology nodes and deliver application-specific integrated circuits and systems on a chip. You will drive reliable products by optimizing, analyzing, customizing, and verifying our power delivery network to meet performance and integrity specifications. You will perform technical evaluations of process nodes, metal stacks, electronic design automation tools, and intellectual properties, and provide recommendations. You will develop power delivery and reliability solutions and methodologies that co-optimize across the entire design space, then see these through from inception to maturity and tapeout.

The US base salary range for this full-time position is $163,000-$237,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Responsibilities

• Drive early process and metal stack analysis.
  Influence power architecture, including unique power rails, domain boundaries, block pitch, through-silicon via plans, routing resources, and voltage budgets.
• Design and deliver power grid designs for all power domains and intellectual properties, meeting power density and integration requirements, including custom power grids for power-critical blocks.
• Co-optimize through-silicon via and power grid on 3D stacked dies. Optimize tracks to ensure design rule check cleanliness, maximize routing resources, incorporate metal-insulator-metal insertion, and augment power grids to improve electromigration and IR drop.
• Collaborate with clock, full-chip, physical design flow owners, and package, bump, and redistribution layer designers to co-optimize designs and accommodate top-level routes.
• Stabilize and finalize power grid designs aligned to project milestone requirements, including comprehensive design rule check clean-up.