Cadence Design Systems

Principal Design Engineer

Cadence Design Systems • $120K — $150K *
Austin, TX 78745In-Person
Information Technology
5 - 7 years of experience
Today
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Job Overview by Ladders

Qualifications

  • Bachelor's degree in Electronic or Electrical Engineering or related field.
  • Minimum 7 years of experience in design verification or a related role.
  • Experience in writing detailed verification documents and developing test cases.
  • Proficiency in functional verification fundamentals and environment planning.
  • Expertise in UVM for developing functional verification environments.
  • Knowledge of System Verilog Assertions for protocol checks.
  • Ability to debug failures and perform impact analysis on designs.

Responsibilities

  • Research, design, develop, and test electronic systems for EDA and semiconductor IP.
  • Lead verification efforts for Cadence Memory Controller development.
  • Contribute to functional verification of Memory Controller IP.
  • Enhance existing functional verification environments with new features.
  • Ensure clean configurations during verification regressions.
  • Support customers in resolving issues related to the verification environment.
  • Align designs with technical and quality requirements as per established metrics.

Benefits

  • Telecommuting flexibility is available.
Full Job Description
Job Duties:

  • Research, design, develop, and test electronic components and systems for Electronic Design Automation (EDA) and semiconductor intellectual property (IP) employing knowledge of electronic theory and materials properties.
  • Lead the verification effort for Cadence Memory Controller development.
  • Contribute to the functional verification of Cadence's Memory Controller IP.
  • Work with the existing functional verification environment to add new features into the verification environment.
  • Ensure various customer configurations are clean as part of verification regressions.
  • Support customers in case of any issues with using the verification environment and provide functional and code coverage.
  • Ensure that the design is in line with the technical and quality requirements set for the team, particularly with respect to our quality metrics.
  • Some telecommuting permitted.


Qualifications:

  • Bachelor's degree in Electronic Engineering, Electrical Engineering, or related field.
  • Minimum seven (7) years of progressive, post-baccalaureate experience in the job offered or in a related occupation.
  • Design verification including writing detailed verification documents, test case development, and checking test results
  • Functional verification fundamentals, environment planning, test plan generation, and environment development
  • Universal Verification Methodology (UVM) based functional verification environment development
  • System Verilog Assertions (SVA) for protocol checker development
  • Debug failures and report issues found in design
  • Functional coverage analysis and closure

About Cadence Design Systems

Cadence Design Systems, Inc. is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
Learn more about Cadence Design Systems
Size
9,300 employees
Market Cap
$43.9 billion
Industry
Enterprise Technology
Net Income
$590.6 million
Founded
2018
5 Year Trend
+10.5%
Revenue
$2.6 billion
NASDAQ
CDNS
* Ladders Estimates

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