Master's degree and/or PhD in Electrical Engineering or related fields
5+ years of experience in PLL design and production level tape-out experience
Extensive experience with advanced node technologies (16nm to 2nm processes)
Deep understanding of phase noise analysis and VCO design
Proficient in Cadence Virtuoso and electromagnetic simulators (e.g., EMX/HFSS)
Responsibilities
Understand trade-offs between various PLL topologies according to specifications
Architect, design, and simulate analog/mixed-signal PLL components at transistor level
Address advanced node challenges like self-heating and device-level noise optimization
Supervise layout verification to ensure effective floor planning and matching
Conduct PLL bring-up and performance characterization in the lab
Perform comprehensive system-level simulations for PLL integration
Benefits
Opportunity to work with cutting-edge technology in advanced node processes
Involvement in comprehensive system-level projects
Supervisory role over layout verification, enhancing leadership skills
Access to state-of-the-art lab equipment for performance characterization
Collaboration on innovative solutions in a dynamic team environment
Full Job Description
What You Will Do:
Understand trade-offs between different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range
Architect, design and simulate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) at transistor level using tools like Cadence Virtuoso and Spectre
Address challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization
Supervise and verify layouts produced by layout engineers to ensure floorplanning, matching, and parasitic minimization using advanced node technologies
Be responsible for PLL bring up in the lab, conducting performance characterization using state-of-the-art lab equipment
Conduct comprehensive system-level simulations and validation for PLL integration into advanced transceiver technologies
What You Will Bring:
Master's degree and/or PhD in Electrical Engineering or related fields with 5+ years of relevant experience in PLL design, and production level tape-out experience.
Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
Deep understanding of phase noise analysis, VCO design, LDOs and supporting circuitry associated with PLLs
Proficient in cadence virtuoso, electromagnetic simulator (e.g., EMX/HFSS), and MATLAB for system-level modelling
Strong communication and documentation skills
Salary Range
$150,000 - $250,000 Annually The final offer will be determined based on job-related skills, experience, qualifications, and location.
