Your Team, Your Impact

Join Marvell's Custom Compute Solutions Business Unit (CCSBU) as we establish our design presence in San Diego's thriving semiconductor ecosystem.

This team will be responsible for delivering high-quality customer silicon for advanced AI, XPU, and XPU-Attach programs. By partnering closely with customers and internal stakeholders, the design center will enable Marvell's most strategic and financially significant custom SoC initiatives, delivering differentiated solutions that reinforce Marvell's position as a trusted partner for next-generation compute platforms.

This is a rare career opportunity. You're not joining an established local team - you'll be part of building one. You'll define the culture and shape the technical DNA of Marvell's San Diego design organization.

What You Can Expect

• Design, develop, implement, verify, and document micro-architecture and RTL for complex power management integrated circuits.
• Work closely with system and chip architects to design industrial quality implementations.
• Participate in the full design development cycle, end-to-end, from writing micro-architecture docs, RTL coding, specifications of timing, closely work with design verification teams to review test plans and execution of test, ability to bring up block tests on silicon during lab testing, and maintenance of designed blocks and reusable IPs.
• Produce comprehensive block uArchitecture and register Specs.
• Schedule detailed reviews with cross-functional teams
• Evaluate and participate in improving design and verification methodologies.

What We're Looking For

Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10+ years of related professional experience. Or Master's/PhD in Computer Science, Electrical Engineering or related fields with 3-5+ years of experience.

To be successful in this role you will need the following skills:

• Strong background in SystemVerilog RTL coding techniques.
• Experience in high speed, multiple clock domain designs
• Familiar with modern SoC architectures and various interface technologies such as AXI, DDR, Ethernet, PCIe.
• Experience in micro-architecture of complex custom/ASIC products involving Chip I/O, shared memory, and embedded processors
• RTL design experience, synthesis, static-timing closure, formal verification, gate-level simulations, and block-level functional verification.
• Experience in implementation/timing closure for high speed design.
• Ability to create SVA assertions and apply formal verification concepts and tools
• Ability to come up with creative and innovative solutions, and display technical leadership from within a team of engineers
• Excellent verbal and written communication
• Discipline and rigor in documentation
• Ability to work efficiently and influentially with team members across multiple sites
• Enthusiastic about exploring and applying new methods, tools, and process efficiency to ASIC design flow
• Knowledge of scripting languages such as Python, Perl, Tcl, and UNIX shell is desirable.

Expected Base Pay Range (USD)
135,900 - 201,130, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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