About the role- Lead the micro-architecture and RTL design for Mixed-Signal chiplet focused on intelligent power optimization solutions for AI and high-performance computing.
What you'll do- Architect, model, and implement digital PID / cascade control loops (voltage-mode, current-mode, or hybrid) for high-frequency multi-phase IVRs.
- Develop micro-architecture and implement RTL for control of mixed-signal circuits
- Translate validated MATLAB/Simulink controller models into production-quality RTL (Verilog / SystemVerilog) using HDL Coder or manual high-quality coding.
- Design and implement supporting digital blocks: ADC interface, DPWM (digital PWM),
- Perform closed-loop stability analysis on switched power stages.
- Collaborate closely with analog designers on loop compensation, sensor design, quantization effects, and delay budgeting.
- Analyze and optimize for area, power, timing, and metastability in the digital controller across PVT corners.
- Support silicon bring-up, debug, and controller tuning on lab hardware.
WhatWe're Looking For - Strong mixed-signal background: Solid understanding of both analog power circuits (buck converters, 3-level buck, hybrid SC-inductor topologies) and digital control systems, digital filters etc.
- Expert-level MATLAB / Simulink experience:
- Proven experience converting MATLAB/Simulink control algorithms into clean, synthesizable RTL (HDL Coder or hand-coded Verilog/SystemVerilog).
- Deep knowledge of digital PID implementation challenges: quantization, sampling effects, computational delay, fixed-point arithmetic, and limit cycling.
- Familiarity with high-frequency power converter control and digital PWM modulators (DPWM).
- Experience with mixed-signal verification flows (analog-digital co-simulation).
- Good understanding of analog effects impacting digital control: loop delay, sensor non-idealities, inductor non-linearities, PDN resonances.
- Proficiency in digital design tools: Synopsys VCS, Verdi, Design Compiler, PrimeTime (or equivalent Cadence flow).
- BSEE / MSEE or PhD with 8+ years of relevant experience in power management ICs or high-performance mixed-signal design.
Nice to Have - Prior experience designing digital controllers for integrated voltage regulators (IVRs), point-of-load (PoL) converters, or high-current AI/HPC power delivery.
- Knowledge of advanced topologies: 3-level buck, multi-level converters, hybrid switched-capacitor + inductive converters.
- Experience with package-integrated magnetics, high-permeability materials, and PDN modeling (Ansys Q3D / SIwave).
- Experience with formal verification or assertion-based mixed-signal verification.
READY TO JOIN?The pay range for this role is:
175,000 - 350,000 USD per year (San Jose (HQ))
