Advanced Micro Devices, Inc

Lead Design Verification Engineer-Memory Controller

Advanced Micro Devices, Inc • $150K — $180K *
San Jose, CA 95123In-Person
Information Technology
Less than 5 years of experience
Today
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Job Overview by Ladders

Qualifications

  • 8+ years of experience with a BS, 6+ years with an MS, or 3+ years with a PhD in Electrical Engineering, Computer Engineering, or Computer Science.
  • Hands-on experience with state-of-the-art memory controllers like DDR, LPDDR, and HBM.
  • Proven technical leadership of teams with 5 or more engineers.
  • Experience developing UVM and System Verilog test benches, and using simulation tools like Synopsys VCS or Cadence Xcelium.
  • Strong understanding of advanced verification techniques, including assertion and metric-driven verification.

Responsibilities

  • Lead the verification of high-speed Crypto and NoC designs, ensuring quality and performance.
  • Architect and develop simulation and formal-based verification environments at IP and SoC levels.
  • Manage verification teams through planning, execution, tracking, and delivery processes.
  • Develop comprehensive verification plans, including testbenches and test cases.
  • Collaborate with cross-functional teams to define and implement verification strategies.
  • Utilize advanced verification methodologies such as UVM and formal verification.
  • Mentor junior engineers and foster a collaborative team environment.

Benefits

  • Comprehensive healthcare options including medical, dental, and vision coverage.
  • 401(k) plan with matching contributions to support retirement savings.
  • Paid time off for personal time, holidays, and vacation.
  • Employee discounts and perks.
  • Opportunities for professional development and continuous learning.
Full Job Description
THE ROLE:

Adaptive and Embedded Computing Group (AECG) seeks a Senior Staff Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of cutting-edge DRAM Memory Controller IPs (DDR5, LPDDR6, HBM4), high-speed Crypto, and Network-on-Chip (NoC). You will be responsible for architecting, developing, and utilizing simulation and/or formal-based verification environments at both block and SoC-level to achieve first-pass silicon success.

THE PERSON:

The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre-Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality.

Key Responsibilities:
  • Lead the verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (DDR5, LPDDR6, HBM4) designs, ensuring the highest standards of quality and performance.
  • Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level.
  • Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs.
  • Develop and execute comprehensive verification plans, including testbenches and test cases.
  • Collaborate with design, architecture, and software teams to define and implement verification strategies.
  • Utilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification.
  • Mentor and guide junior engineers, fostering a collaborative and innovative team environment.


PREFERRED EXPERIENCE:
  • Require hands on experience with verification of state-of-the-art memory controllers such as DDR, LPDDR, and HBM. Requires strong understanding of current memory controller protocols and calibration (DDR3/4/5, LPDDR4/5/6, HBM2/3/4), board skew and jitter modeling.
  • Require proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs.
  • Require experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium.
  • Require strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance IP and/or VLSI designs is a plus.
  • Require familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management.
  • Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus.
  • Experience with gate-level simulation, power-aware verification is a plus.
  • Experience with silicon debug at the tester and board level, is a plus.


ACADEMIC CREDENTIALS:

  • Require BS w/ 8+ yrs or MS w/ 6+ yrs or PhD w/ 3+ yrs in Electrical Engineering, Computer Engineering, or Computer Science.

This is a 5 Day per week onsite role in San Jose.

This role is not eligible for visa sponsorship.

#LI-RL1

Benefits offered are described: AMD benefits at a glance.

About Advanced Micro Devices, Inc

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Join a team of over 12,000 dedicated professionals at the intersection of technology, industry expertise, and digital innovation. At AMD, you will work on groundbreaking projects that shape the future of computing and graphics. Our collaborative environment encourages networking and the sharing of ideas across teams and disciplines.

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Learn more about Advanced Micro Devices, Inc
Size
15,500 employees
Market Cap
$100.9 billion
Industry
Manufacturing & Automotive
Net Income
$2.4 billion
Founded
1969
5 Year Trend
+30.9%
Revenue
$9.7 billion
NASDAQ
AMD
* Ladders Estimates

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