Your Team, Your Impact

As a key CAD member of Marvell Central Engineering, you will play a leading role on developing next-generation automated design flow and its add-on tools. You will have the opportunity to use your extensive design and CAD knowledge to participate in defining the whole organization's design infrastructure, methodology and workflows.

What You Can Expect

In this role you will:
• Develop and maintain leading-edge CAD flows addressing the needs of Marvell's various Business Units.
• Contribute to the deployment and support of highly modular and automated CAD flows.
• Work in collaboration with the infrastructure and flow teams to ensure optimal integration within the overall CAD platform.
• Come-up with innovative solutions to ever-increasing design challenges.
• Drive stakeholders' alignment across multiple BUs over key CAD architectural decisions.

What We're Looking For
• Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience. OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
• Solid understanding and executional experience with the following:

• Good level in scripting in Tcl and Python in the context of flow development.
• Proficiency in Verilog / System Verilog Design and Verification.
• Experience in RTL linting tools, including clock domain crossing (CDC).
• Experience in git revision control.
• Knowledge in Equivalence Checking for both RTL to gates and gates to gates in LEC or in Formality is highly desirable
• Demonstrate good analysis and problem-solving skills. Out-of-the-box thinking.
• Team player with good verbal and written communication skills.
• A keen eagerness to learn new skills is also important.

Preferred Qualifications:

• Experience in RTL linting tools, including clock domain crossing (CDC)
• Knowledge in UPF definition and multiple power domains implementation
• RTL qualification, integration and release process
• Knowledge in writing, validating and debugging timing constraints (SDC)
• Knowledge in Synthesis tools, and downstream integration with P&R tools.
• Implementing Functional ECOs, ideally having setup ECO flows, either LEC eco or Formality ECO

Expected Base Pay Range (USD)
150,680 - 225,700, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

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