NXP Semiconductors

Digital Design Flow Architect

NXP Semiconductors • $160K — $190K *
San Jose, CA 95123In-Person
Information Technology
Less than 5 years of experience
Today
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Job Overview by Ladders

Qualifications

  • B.S. in Electrical Engineering, Computer Engineering, Computer Science, or related field required; M.S. or Ph.D. preferred.
  • Director-level technical leader with digital design, CAD/methodology, and EDA implementation experience.
  • Proven ability to influence senior stakeholders and lead cross-functional transformations.
  • Deep hands-on experience with end-to-end digital implementation and RTL-to-GDS flows.
  • Strong expertise in synthesis, timing analysis, and power optimization.
  • Hands-on experience with AI workflows and automation scripting using Tcl, Python, or Perl.
  • Experience with major EDA ecosystems such as Synopsys or Cadence.

Responsibilities

  • Architect a modular RTL-to-GDS digital design flow covering all aspects from synthesis to GDS delivery.
  • Enable AI-assisted debugging and automated analysis in EDA workflows.
  • Establish metrics and standard practices for traceable flow management.
  • Collaborate with design and EDA teams to deploy new technology flows.
  • Enhance productivity and quality through automation and scalable methodologies.

Benefits

  • Collaborative work environment with cross-functional teams.
  • Opportunity to influence technical direction at a high level.
  • Access to cutting-edge technology and EDA tools.
  • Focus on professional growth and continuous learning.
Full Job Description
Role Overview

The Digital Design Flow Architect will define and deploy a repeatable, traceable, and customizable end-to-end digital design flow for advanced process technologies. The role combines RTL-to-GDS implementation expertise, static verification, PPA optimization, AI tool enablement, and hands-on agentic flow development.
Key Responsibilities
  • Architect a modular RTL-to-GDS flow supporting synthesis, place and route, timing/power closure, static verification, signoff, and GDS delivery.
  • Enable agentic execution, AI-assisted debugging, design-space exploration, and automated analysis loops for EDA workflows.
  • Establish repeatable and traceable flow practices, including standard recipes, configuration baselines, metrics, dashboards, audit trails, regression checks, and release management.
  • Deploy flows for new process technologies in partnership with design, CAD/methodology, foundry, and EDA vendor teams.
  • Improve productivity, turnaround time, quality-of-results, and PPA through automation, methodology tuning, and scalable reuse.


Education and Experience Level
  • Education: B.S. in Electrical Engineering, Computer Engineering, Computer Science, or related field required; M.S. or Ph.D. preferred.
  • Level: Director of Technology-level technical leader of digital design, CAD/methodology, EDA implementation, or flow architecture experience.
  • Scope: Proven ability to set technical direction, influence senior stakeholders, and lead cross-functional flow transformation across functional domains or technology nodes.
Required Experience and Skills
  • Deep hands-on experience in end-to-end digital implementation, RTL-to-GDS, static design and timing analysis, formal/static verification, signoff, ECO, and PPA closure.
  • Strong expertise in synthesis, floorplanning, place and route, clock-tree synthesis, power optimization, congestion analysis, and advanced-node implementation challenges.
  • Hands-on agentic AI workflow development experience, including task planning, tool invocation, result interpretation, retry logic, human-in-the-loop checkpoints, and autonomous execution patterns.
  • Practical MCP experience, including MCP clients/servers, tool and resource exposure, secure access, JSON-RPC-style communication, and integration with engineering systems.
  • Strong scripting and automation skills using Tcl, Python, Perl, shell, or equivalent flow automation technologies.
  • Experience with major EDA ecosystems such as Synopsys, Cadence, Siemens EDA, or equivalent internal platforms.
  • Ability to translate design challenges into repeatable methodology improvements, reusable automation, and measurable productivity gains.
  • Experience defining and executing deployment and migration strategies from current script-driven digital design flows to goal-driven agentic flows, including phased rollout, MCP/tool-adapter integration, validation against golden flows, human-in-the-loop checkpoints, observability, governance, rollback planning, and production adoption across RTL-to-GDS workflows.
Preferred Qualifications
  • Experience with AI-enabled EDA, agent orchestration, retrieval-augmented generation, multi-agent workflows, and workflow state management.
  • Experience developing MCP-enabled connectors or tool adapters for EDA tools, job schedulers, dashboards, repositories, databases, or compute environments.
  • Experience building production-quality flows with observability, auditability, permission control, evaluation harnesses, regression validation, documentation, and release management.


More information about NXP in the United States...

About NXP Semiconductors

NXP Semiconductors N.V. is a Dutch semiconductor manufacturer with headquarters in Eindhoven, Netherlands. The company employs approximately 31,000 people in more than 35 countries, including 11,200 engineers in 33 countries. NXP reported revenue of $8.88 billion in 2020. The company's products are used in a wide range of automotive, identification, wireless infrastructure, lighting, industrial, mobile, consumer and computing applications. NXP is the co-inventor of near field communication (NFC) technology along with Sony and supplies NFC chip sets that enable mobile payments, as well as secure access to cars and buildings.
Learn more about NXP Semiconductors
Size
31,000 employees
Market Cap
$39.8 billion
Industry
Manufacturing & Automotive
Net Income
$52 million
Founded
1953
5 Year Trend
+3.1%
Revenue
$8.6 billion
NASDAQ
NXPI
* Ladders Estimates

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