Advanced Micro Devices, Inc

DFx Methodology Architect

Advanced Micro Devices, Inc$130K — $180K *
Consumer Technology
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • 5-7 years of experience in DFx architecture, RTL design and methodology development
  • Strong background in Power, Performance, and Area (PPA) optimization
  • Proficient with RTL implementation in Verilog/SystemVerilog
  • Experience in timing and design quality checks for DFx-IPs
  • Familiarity with Siemens Tessent DFT flows and associated standards
  • Strong foundation in logic design and timing methodologies
  • Ability to mentor and lead cross-functional teams effectively.

Responsibilities

  • Define and lead DFx architecture and specifications for SoC and DFx-IPs
  • Document DFx architecture interactions with hardware and firmware
  • Implement DFx features in RTL using Verilog/SystemVerilog
  • Oversee timing and design quality checks for DFx-IPs
  • Collaborate with execution and verification teams for DFx-IP integration
  • Coordinate with design teams for verification test plans and timing targets
  • Engage with validation teams on test plans and silicon debug
  • Contribute to advancements in front-end, DFx, and timing methodologies.

Benefits

  • Comprehensive health and wellness benefits
  • Retirement savings plan with company match
  • Employee stock purchase plan
  • Flexible working arrangements
  • Opportunities for professional development and training.
Full Job Description
THE ROLE:

AECG organization at AMD is looking for an experienced DFx Architecture, Methodology and Logic Design Expert with strengths in RTL and Timing to support FPGA-SoCs and custom ASICs. In this role, you will own and drive DFx Architecture definition, RTL implementation and methodology development.

THE PERSON:

You have had significant success driving Architecture, Design Methodologies, RTL, and Timing to tape out and production. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This role will stretch you as you lead design teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design, verification, validation, CAD and product engineering teams. You have excellent communication, presentation and problem-solving skills. The candidate should be comfortable working hands-on. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

KEY RESPONSIBILITIES:
  • Define and lead SoC-DFx Architecture, Specifications and development of DFx-IPs
  • Own DFx Architecture documentation, accounting for interactions with other features, the hardware and the firmware
  • Implement DFx features in RTL using Verilog/SystemVerilog
  • Co-owning Timing and Design Quality Checks (and waivers) for the DFx-IPs
  • Work cross functionally with DFx execution and verification teams to enable integration and validation of DFx-IPs in all phases of design implementation flow
  • Work closely with Design teams for Verification Test plan reviews, Timing targets and Performance/Power Verification sign offs
  • Engage with validation and product teams on test plan, coverage, Silicon bring up and silicon debug
  • Contribute to front-end, DFx and timing methodologies
  • Drive innovation in a rapidly changing technological environment


PREFERRED EXPERIENCE:
  • Proficient with Siemens Tessent DFT flows, such as Tessent Shell, Tessent Scan, Tessent ATPG, Tessent MemoryBist, IJTAG and SSN
  • Understanding of 1149.1 / 1687 standards, understanding of ATPG, experience in 2.5D and 3D IC testing
  • Strong understanding of DFT Architecture and Debug methodologies
  • Strong foundation in logic design, switching theory and timing
  • Experience with supporting silicon debug and diagnosis
  • Skilled at collaborating with teams across different geographies
  • Scripting language experience: Perl, Python and TCL
  • Exposure to leadership or mentorship is an asset


ACADEMIC CREDENTIALS:
  • Bachelors or Masters or PhD degree in computer engineering/Electrical Engineering


This role is not eligible for visa sponsorship.

#LI-CJ3

#LI-Hybrid

Benefits offered are described: AMD benefits at a glance.

About Advanced Micro Devices, Inc

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Learn more about Advanced Micro Devices, Inc
Size
15,500 employees
Market Cap
$100.9 billion
Industry
Net Income
$2.4 billion
Founded
1969
5 Year Trend
+30.9%
Revenue
$9.7 billion
NASDAQ

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