Advanced Micro Devices, Inc

CPU Core Design Verification Engineer

Advanced Micro Devices, Inc$110K — $130K *
Consumer Technology
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • 5-7 years of experience in CPU core design verification or related fields
  • Proficiency in C++ and SystemVerilog for developing testbench components
  • Solid understanding of computer architecture and processor microarchitecture
  • Experience with digital logic design and RTL concepts using Verilog
  • Familiarity with constrained-random testing and coverage-driven verification
  • Ability to perform root-cause analysis for simulation failures
  • Knowledge in scripting languages like Python or Perl is a plus

Responsibilities

  • Collaborate with cross-functional teams to understand microarchitectural features and verification needs
  • Own and manage the entire testing cycle for assigned verification portions
  • Design and maintain modular C++ and SystemVerilog testbench components
  • Write and supervise SystemVerilog assertions and coverage models
  • Independently debug simulation failures and resolve issues with RTL or testbench
  • Drive coverage closure and enhance verification methods when necessary
  • Utilize AI-assisted tools to boost verification efficiency

Benefits

  • Comprehensive health benefits
  • 401(k) retirement plan
  • Flexible work hours and hybrid work options
  • Employee stock purchase plan
  • Tuition reimbursement programs
  • Professional development opportunities
  • Employee wellness programs
Full Job Description
THE ROLE:

As a CPU Core Design Verification Engineer, you will verify new and existing microarchitectural features in AMD's next-generation x86 CPU cores. Working within a C++ and Verilog/SystemVerilog-based environment, you will independently own a portion of the unit- or core-level verification effort - developing tests, checkers, and coverage and driving them to a quality result with limited supervision.

You will collaborate with RTL designers, architects, and fellow verification engineers, both within the verification team and across departments, to ensure microarchitectural intent is correctly implemented and validated. Success requires solid computer architecture fundamentals, the ability to analyze and evaluate microarchitectural behavior using standard verification methods, and a self-motivated approach to owning the quality and timeliness of your work.

THE PERSON:

You have a strong interest in computer architecture and processor microarchitecture and enjoy working at the intersection of hardware and software. You are a self-motivated problem solver who takes responsibility for the quality and timeliness of your portion of the project, planning your work over a horizon of weeks to months.

You value clean, scalable verification environments and apply sound testbench and agent principles in your work. You make technical decisions independently within your area, put checks and balances in place to catch issues early, communicate clearly, and collaborate effectively across teams and time zones.

KEY RESPONSIBILITIES:
  • Collaborate with RTL designers, architects, and verification engineers to understand microarchitectural features, corner cases, and verification requirements
  • Own the test plan, stimulus, checking, and functional coverage for an assigned portion of unit- or core-level verification
  • Design, implement, and maintain C++-based and SystemVerilog-based testbench components, applying modular, reusable verification agent patterns
  • Write and maintain SystemVerilog assertions and functional coverage models
  • Debug simulation failures, independently drive root-cause analysis, and work cross-functionally to resolve RTL or testbench issues
  • Drive functional and code coverage closure for your area, identify verification gaps, and improve stimulus and checking as needed
  • Apply AI-assisted and agent-based development tools to improve verification productivity

PREFERRED EXPERIENCE:
  • Good understanding of computer architecture
  • Experience using C++ and SystemVerilog to develop verification infrastructure for complex hardware designs
  • Working knowledge of Digital Logic Design and RTL design concepts using Verilog
  • Familiarity with constrained-random testing and coverage-driven verification
  • Understanding of assembly-level programming and instruction execution at the ISA level
  • Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics
  • Scripting knowledge (Python, Perl) is a plus

ACADEMIC CREDENTIALS:
  • Bachelors or Masters degree in computer engineering/Electrical Engineering

LOCATION: Austin, TX

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Benefits offered are described: AMD benefits at a glance.

About Advanced Micro Devices, Inc

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Learn more about Advanced Micro Devices, Inc
Size
15,500 employees
Market Cap
$100.9 billion
Industry
Net Income
$2.4 billion
Founded
1969
5 Year Trend
+30.9%
Revenue
$9.7 billion
NASDAQ

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