Job Description
JOB DUTIES:
Defining and implementing test plans, developing System Verilog /UVM based unit level test benches, including stimulus, checkers, monitors and assertions, analyzing and debugging regression fails, and developing and analyzing functional coverage on North Bridge / Data Fabric Design.
Key skills are software (System Verilog, C/C++, object oriented programming, scripting (e.g. Perl), x86 assembly), Verilog simulation and modeling, knowledge of computer and peripheral architectures.
EXPERIENCE AND EDUCATION:
Bachelors and 0-2 years experience, or Masters and 2+ years experience; Requires demonstrated technical expertise in functional verification of microprocessor designs; Experience with Verilog, System Verilog, UVM, programming in Perl & C/C++, logic simulation is a requirement; Requires very strong understanding of computer architecture; Experience of assertion based design strategies, code coverage, functional coverage etc will be an asset; Requires good communication and technical leadership skills
Test Engineer with following qualifications:
B.S. or equivalent in Mechanical Engineering, Thermal Engineering, or equivalent technical field.
Strong background in thermodynamics, fluid mechanics, heat transfer and numerical methods.
Experience with instrumentation, data collection, and post-processing, i.e. LabVIEW and/or various DAQ systems,
Experience with temperature, pressure, velocity and flow rate measurements.
Familiar with using lab equipment tools ie.. multimeter scope, power supply, thermocouples, airflow chamber, pressure gauge, flow meter)
Ability to perform assembly or tear down of products/testing boards in order to do testing, evaluation, and analysis.
2-3 years (preferred) of research and/or engineering experience following graduate studies.
Experience with using thermal modeling CAD tools
Top Skills:
Focus in thermal background with understanding of mechanical.
Testing and lab experience/skills
Thermal modeling and Simulation skills
