SystemC Modeling Developer Key Responsibilities Develop SystemC/TLM2.0-based functional, timing, and performance models for server subsystems (CPU, memory, I/O, accelerators, AI engines). Build modular, scalable models for Compute & AI workloads and integrate them into simulation frameworks. Perform system-level performance modeling, profiling, and bottleneck analysis across compute, memory, and accelerator paths. Support pre-silicon BIOS, firmware, and driver enablement using virtual platforms. Validate models against RTL or hardware references to ensure functionality and accuracy. Work with simulators such as Synopsys Virtualizer, Cadence VSP, QEMU-based frameworks, etc. Collaborate with architects, RTL designers, platform engineers, and performance teams to align modeling results with product goals. Document model features, APIs, interfaces, and usage workflows for internal teams. Required Qualifications Strong hands-on experience with SystemC, TLM2.0, and C/C++. Solid understanding of computer architecture including CPU pipelines, cache hierarchy, memory controllers, PCIe/CXL, and AI/compute subsystems. Experience in cycle-accurate, timing-accurate, or transaction-level modeling. Knowledge of pre-silicon simulation flows and virtual platform development. Ability to analyze performance data, interpret system behavior, and provide optimization insights. Strong debugging skills in complex simulation environments. 8+ years of experience in SystemC/TLM modeling, pre-silicon simulation, or architectural modeling for semiconductor/server platforms. Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field. Preferred Qualifications Experience modeling AI/ML accelerators, GPUs, or heterogeneous compute units. Familiarity with server-class SoC architectures (x86, ARM, RISC-V). Exposure to firmware/BIOS bring-up using virtual models. Knowledge of RTL design (SystemVerilog) or hardware emulation (optional). Experience with performance tools, trace-driven analysis, or workload modeling. Understanding of high-speed interfaces (PCIe, CXL, NVMe, Ethernet). 4+ years of experience in Hardware Description Languages (HDLs): VHDL or Verilog. 5+ years of experience in Python.