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X In accordance with Washington state law, we are highlighting our comprehensive benefits package, which is available to all eligible US based employees. Benefits for this role include:

• Health, dental, vision, life, disability insurance
• Retirement Benefits: 401(k) with company match
• Paid Time Off: 20 days of vacation per year, accruing at a rate of 6.15 hours per pay period for the first five years of employment
• Sick Time: 40 hours/year (increased to 69 hours/year for Seattle) including 5 discretionary sick days per instance
• Maternity Leave (Short-Term Disability Baby Bonding): 28-30 weeks
• Baby Bonding Leave: 18 weeks
• Holidays: 13 paid days per year

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Sunnyvale, CA, USA; Kirkland, WA, USA.

Minimum qualifications:

• Bachelor's degree or equivalent practical experience.
• 8 years of experience programming in C or Python.
• 5 years of experience testing, and launching software products.
• 5 years of experience with performance, large-scale systems data analysis, visualization tools, or debugging.
• 3 years of experience with software design and architecture.

Preferred qualifications:

• Deep technical proficiency ML workload performance modeling on pre-silicon systems, familiarity with high level compiler intermediate representations (e.g., MLIR dialects, XLA, HLO), ML execution frameworks (JAX, PyTorch, PyTorch/XLA), or accelerator kernel programming (Pallas, Triton, CUDA).
• Demonstrated track record of architecting, validating, or extending high-performance simulation tools, emulation frameworks, or analytical performance modeling pipelines (e.g., roofline models, cycle-accurate or compiler-aware simulators).
• Proven L6-level ability to lead complex, multi-quarter technical initiatives across distinct organizational boundaries (e.g., hardware design, compilers, AI research, and cloud infrastructure).

About the job

With your technical expertise you will manage project priorities, deadlines, and deliverables. You will design, develop, test, deploy, maintain, and enhance software solutions.

The MARC (Model Architecture and Realizable-performance Co-design) team is Google's proactive, ahead-of-silicon co-design engine. We operate at the critical intersection of frontier ML workloads and multi-year TPU silicon roadmaps. Given rapid 6-month model breakthroughs and complex Compound AI Systems, our mandate is to focus on the 12 month time window between Hardware Architecture Freeze and Physical Silicon Pilot.

In this role, you will define and own the strategy for enabling open-source ML models to achieve TPU performance with internal models at launch. You will establish a principled, scalable methodology to analyze mapping gaps across open-source model families.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $207000 - $300000 (USD) 20% bonus target equity benefits

Learn more about benefits at Google .

Responsibilities

• Deliver certified performance ladders 6 months pre-pilot as the canonical goals for pricing, capacity planning, and XLA/kernel optimization.
• Adapt emerging open-source models into TPU-native twin variants (MaxTwin, sparsity) to prove asymmetric TPU superiority.
• Ingest and optimize multi-turn agentic workflows, reasoning loops, and prompt/decode disaggregated topologies ahead of silicon.
• Author high-signal reference implementations (PyTorch/JAX/Pallas) that guarantee reachability of pre-pilot goals under real-world compiler constraints.
• Partner with L7-L9 leaders across TPU Hardware, XLA Compiler, and Cloud AI Systems to steer multi-year roadmaps.