The Role
The Algorithmic Solutions Group develops cutting-edge, efficient algorithms to bring intelligence to the physical world. We fuse state-of-the-art machine learning with deep domain expertise to convert raw physical data into actionable insights, solving the hard problems where off-the-shelf solutions fall short.
We are seeking aStaff Research Scientist, AI-Hardware Co-Design to architect the solutions that power the next generation of intelligent systems. Through rigorous analysis and proof-of-concepts, you will bridge the gap between advanced AI algorithms and hardware implementation to define the optimal compute strategy. Operating at the boundary of software and silicon, you will drive the co-design of algorithms and architecture, defining the computational foundation to enable physical intelligence.
Key Responsibilities
- Strategic Problem Definition:Collaborate with business leads and domain experts to identify opportunities whereintelligent systems1tegrating sensing, actuation, and tightly coupled algorithms1can solve previously impossible problems. You will focus on challenges that requireholistic system innovationrather than just off-the-shelf components.
- Research-to-Product:Lead technical execution fromarchitectural designto validated proof-of-concept. You will partner with researchers and hardware engineers to bridge the gap betweenabstract research ideasanddeployable solutions.
- Feasibility analysis:Act as the "Physics of Compute" anchor for the research team. You will use high-fidelity simulation, modeling, and proof-of-concepts to quantify the impact of memory hierarchy, dataflow, and precision on system performance1stinguishing between viable product paths and impractical research concepts.
- System-Level Architecture & Co-Design:Drive the simultaneous optimization of algorithms and hardware. You will treat the algorithm and the compute engine as a unified design space, adapting neural architectures to exploit specific hardware capabilities while selecting the optimal compute substrate1rom ultra-low-power MCUs to custom acceleratorsto meet strict power and area constraints.
- Thought Leadership:Maintain a deep awareness of the evolving AI hardware and algorithm landscape. You will bring the best ideas from the academic and industrial communities into ADI, mentoring junior engineers and guiding the team toward state-of-the-art compute paradigms.
The Ideal Candidate
You are aComputer Architectwith a deep appreciation for AI, or anAI Researcherwith a deep understanding of silicon. You think in terms of data movement, memory bandwidth, and energy-per-operation. You understand that hardware constraints shape algorithmic innovation, just as algorithmic needs must dictate architectural choices.
- Educational & Professional Background:You hold a PhD specialized in Computer Architecture or Integrated Circuit Design for AI workloads, and have 3+ years of industry experience applying architectural principles to real-world engineering constraints.
- Deep System-Level Hardware Expertise:You possess a profound understanding of how to organize computation and data. You have demonstrated this by either leading the design of complex AI SoCs, or by validating novel architectures through rigorous,cycle-accurate simulation. You operate at thestructural levelof the machine, optimizing memory hierarchies, on-chip networks, and execution models to solve complex data movement and efficiency challenges.
- Edge AI & Model Optimization:You possess deep expertise inhardware-aware deep learning. You are proficient inmodern frameworks (PyTorch, JAX)and capable oftraining or fine-tuning modelsto validate architectural hypotheses. You go beyond standard backbones to master theoptimal mapping of computational graphs to silicon, orchestrating dataflow, tiling, and quantization (INT8, mixed-precision) to maximize arithmetic intensity within strict edge power budgets.
- Innovation Mindset:You navigate the ambiguity of early-stage innovation with creative persistence, translating open challenges into concrete technical roadmaps. You excel at decision-making under uncertainty, justifying how your architectural trade-offs directly address the problem and create value.
You distinguish yourself with:
- Proven Silicon Execution:You have successfully taped out a complex SoC or a custom AI accelerator. You understand the harsh reality of physical designfrom timing closure to power deliveryand how these downstream constraints influence early-stage architectural decisions.
- DSP & Signal Fluency:You are comfortable discussingFourier transforms, noise floors, and sampling rates. You understand the intersection ofclassical Digital Signal Processing (DSP)and deep learning, capable of architecting systems where neural networks and traditional signal chains work in concert to extract information from noisy physical data.
- Hands-on RTL Experience:Familiarity with Verilog/SystemVerilog or modern hardware construction languages (Chisel, PyMTL) is a strong plus, even if youwill not be writingproduction RTL daily.
- Strong publication record in top conferences and/or journals
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain exportlicensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.As such, applicants for this position 6cept US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) 6ay have to go through an export licensing review process.
Job Req Type: Experienced
Required Travel: Yes, 10% of the time
Shift Type: 1st Shift/Days
The expected wage range for a new hire into this position is $172,000 to $236,500.
Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.
This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.
This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.