Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in high-performance, low-power physical design implementation or design convergence techniques with custom or industry-standard synthesis, PnR, and signoff tools.
• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture (preferred).
• Experience leading cross-functional engineering initiatives across Architecture, RTL, DFT, and Technology (preferred).
• Understanding of power grid design, EMIR constraints, and low-power implementation techniques (preferred).
• Track record of architecting CPU class physical design methodologies or AI/ML-assisted PPA optimization flows (preferred).

Responsibilities

• Lead end-to-end physical design strategy and execution for top-level and critical CPU blocks across advanced process nodes.
• Pioneer novel physical design methodologies, tool flows, and AI/ML optimization techniques to maximize power, performance, and area (PPA).
• Resolve complex timing, power grid, electromigration and IR drop (EMIR), and physical verification bottlenecks in tight iteration loops.
• Drive technical roadmaps, mentor executive engineering peers, and influence architectural trade-offs across cross-functional teams.

Benefits

• Equity options as part of the compensation package.
• Comprehensive health benefits and wellness programs.
• Access to professional development resources and training.
• Flexible working locations in Austin, TX or Mountain View, CA.
• Participate in cutting-edge projects that impact millions of users.