Drive the Next Wave of Computing Innovation at MIPS

At MIPS, we’re shaping the future of compute architecture with advanced IP that powers a wide range of applications. We take a disciplined, methodical approach to designing scalable, energy-efficient solutions that meet demanding power, performance, and area goals.

Our team spans from architecture, performance modeling, design, verification, implementation to software and software optimization for our customers. The team thrives on collaboration, technical depth, and a culture of mutual respect. We value diverse perspectives and practical experience, and we know that excellence is built through thoughtful teamwork and a commitment to the highest engineering standards.

We’re seeking a seasoned CPU microarchitect who brings hands-on RTL development experience and a track record of technical leadership. We’re looking for expertise in one or more of the following areas:

Instruction fetch and branch prediction, instruction decode, scheduling, Out-of-order execution, register renaming, Integer- or floating-point execution, exception handling, Load/store execution, cache design, or memory subsystems

As part of our team, you’ll have the opportunity to take ownership of critical design challenges, mentor colleagues, and contribute to innovations that will define the next generation of MIPS computing solutions.

Essential Responsibilities:

As a CPU microarchitect you own or participate in the following:

• Creation of a microarchitectural specification for a major block from early exploration through micro architectural definition in conjunction with the performance modeling team and arriving at a detailed specification

• RTL design of the major functional block. Ownership includes the design definition, implementation and convergence of the block to project requirements (performance, timing, power, area, schedule)

• Support of the verification team for test bench development, test plan development and test content development, including performance verification

• Work with physical design teams, and design for testability teams to implement and converge physical design and testability

• Minimum BS and 15+ years of relevant industry experience

• Experience with CPU microarchitecture, in at least one of the following areas: instruction fetch, branch prediction, instruction decode, instruction scheduling, out of order execution, register renaming, integer or floating point execution, exception handling, load/store execution, cache design, or memory management unit

• Experience with Verilog, System Verilog, or VHDL

• Experience with commercial simulators and debugging tools

• Expert in logic design

Preferred Qualifications

• Experience with timing, power and area trade-offs in CPU microarchitecture

• Experience with high performance CPU microarchitecture techniques

• Experience with ISAs such as RISC-V, ARM-v8, or x86

• Experience using scripting languages and regular expressions

• Programming experience with assembly, C, or C++

• Experience with emulators is a plus

Expected Salary Range

The exact Salary will be determined based on qualifications, experience and location.