Encore Semi LLC

Sr Physical Design Engineer (Synopsys Fusion / GF 12LP) - Remote - Full Time / Contract

Encore Semi LLC$150K — $165K *
US-AnywhereRemote in Austin, TX
Information Technology
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • 10+ years of ASIC physical design experience with tape-outs on advanced FinFET nodes (14nm/12nm/7nm)
  • Expertise in rapid DRC/LVS/ERC closure and tape-out processes
  • Mastery of Synopsys Fusion Compiler (or ICC2) and PrimeTime
  • Strong scripting abilities in Tcl, Python, and Bash
  • Preferred experience with GlobalFoundries 12LP/12LP+ and Mentor Calibre.

Responsibilities

  • Drive high-speed design tasks to completion, focusing on 1GHz AES hard macro
  • Execute block and top-level physical design using Synopsys Fusion Design Platform
  • Achieve timing closure and signoff using PrimeTime and StarRC across various corners
  • Optimize routing challenges specific to 12nm FinFET technology
  • Perform DRC, LVS, and antenna checks employing Calibre and Synopsys ICV
  • Maintain and enhance automation scripts using Tcl, Python, or Perl
  • Take ownership of RTL-to-GDSII flow for next-gen SoCs focusing on Power, Performance, and Area.

Benefits

  • 15 days of PTO per calendar year
  • 10 paid Holidays per calendar year
  • Comprehensive Medical benefits covering 80% of premiums for employees and their dependents
  • Dental and Vision coverage with 50% premiums covered by the company
  • 401k options including Traditional and Roth
  • Tuition reimbursement
  • Employee Assistance Program (EAP).
Full Job Description
Sr Physical Design Engineer (Synopsys Fusion / GF 12LP) - Remote - Full Time / Contract Full-time: Salary + Benefits + Bonuses / Contractor Work Status: US Citizen or Lawful Permanent Resident. We have an immediate need for an expert Physical Design Engineer to drive a high-speed design across the finish line. You will be working on a 1GHz AES hard macro targeted for the GlobalFoundries 12LP (12nm FinFET) process node. The design is nearly complete; your primary objective upon joining will be the final cleanup of 7 remaining DRC/ERC errors, completing fill insertion, and executing the final Calibre signoff checks for tape-out. Core Technical Environment & Ongoing Responsibilities: Beyond this immediate milestone, you will take ownership of the RTL-to-GDSII flow for our next-generation SoCs, pushing the limits of Power, Performance, and Area (PPA). • Implementation: Execute block-level and top-level physical design (floorplanning, CTS, routing) using the Synopsys Fusion Design Platform (Fusion Compiler). • Timing & Signoff: Drive STA, parasitic extraction, and timing closure across multiple corners using PrimeTime and StarRC. • FinFET Optimization: Address 12nm FinFET challenges including advanced routing rules, EM/IR-drop analysis (Ansys RedHawk), and complex SDC constraint management. • Verification: Perform DRC, LVS, and antenna checks using Calibre and Synopsys IC Validator (ICV). • Automation: Maintain robust Tcl, Python, or Perl scripts to automate workflows. Qualifications: • 10+ years of industry experience in ASIC physical design with successful tape-outs on advanced FinFET nodes (14nm/12nm/7nm). • Deep expertise in rapid DRC/LVS/ERC closure and final tape-out procedures. • Hands-on mastery of Synopsys Fusion Compiler (or ICC2) and PrimeTime. • Strong scripting skills (Tcl, Python, Bash). • Preferred: Direct experience with the GlobalFoundries 12LP/12LP+ node and Mentor Calibre. The anticipated annual base salary for this position is between $150,000 to $165,000, which also includes a comprehensive benefits package. Full-Time Benefits: • 15 days of PTO per calendar year • 10 paid Holidays per calendar year • Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents • Dental & Vision: Company covers 50% of premiums for Employee and Dependents • Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance • Employee Assistant Program (EAP) • 401k - Traditional & Roth • Life/AD&D and Long-Term Disability • Tuition reimbursement LinkedIn :: https://www.linkedin.com/in/rtl2gds/

About Encore Semi LLC

Encore Semi LLC is a semiconductor design and engineering services company that provides custom solutions for complex system-on-chip (SoC) designs. The company was founded in 2013 and is headquartered in San Jose, California. Encore Semi has over 500 employees and serves clients in various industries, including automotive, aerospace, and telecommunications. The company's services include architecture and design, verification and validation, and software and firmware development. Encore Semi is committed to innovation and has received several awards for its services, including the TSMC Open Innovation Platform Partner of the Year Award.
Learn more about Encore Semi LLC
Size
500 employees
Industry
Net Income
$500,000
Founded
2013
5 Year Trend
+30%
Revenue
$50 million

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