Minimum qualifications:- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- Experience with two or more of the following areas: computer architecture, embedded firmware, digital systems, ASIC design, or verification.
- Experience with hardware and software integration or validation.
- Experience with RTL development, design verification, or evaluation.
Preferred qualifications:- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with C /Python software design principles.
- Experience integrating complex hardware/software systems and
experience developing firmware for embedded systems or accelerators. - Proficiency in debugging firmware using simulation tools or working knowledge of RTOS internals.
About the jobIn this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Be part of the TPU team that builds Machine Learning Accelerator ASICs for Google and positively impact Google's products and billions of Google users across the globe.
In this role you will be working on ASIC development, validation, software, tools, and methodologies and have the ability to push the boundaries of chip-development and hardware/software (HW/SW) integration and validation.
Support cross-functional work streams focused on end-to-end HW/SW integration and validation to demonstrate HW, SW, and system functionality and performance. Help the chip team accomplish key silicon development criteria, meet chip and system schedules and achieve readiness for production in various silicon and system validation environments.
You may write firmware, RTL, scripts, or test content to integrate and demonstrate subsystem and system functionality. You will validate this functionality on simulation, emulation, or post-silicon environments.
US: $116000 - $166000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities - Review chip specifications and designs, develop the integration plan with software and system partners, coordinate hardware and software delivery, and demonstrate functionality.
- Assist with the bring-up of machine learning compute features, integrating and validating hardware and software designs, including first-party and third-party intellectual properties, and developing firmware to validate hardware functionality.
- Utilize hardware and software co-simulation methodologies, leveraging register-transfer level (RTL) simulation, emulation, and field-programmable gate array (FPGA) environments as appropriate to correlate performance.
- Assist with debug discussions with design, design verification (DV), software, and architecture teams, helping to root-cause functional failures and performance issues through the product development cycle.
