THE ROLE: The Memory Subsystem team is seeking a UMC Lab Liaison Engineer to drive post-silicon bring-up, debug, and feature enablement for DDR memory subsystems across AMD's next-generation client and server platforms.
This role operates at the intersection of silicon validation, firmware, design, and SoC integration, serving as the technical point-of-contact for UMC-related issues during bring-up and production ramp. The engineer will own end-to-end execution of memory subsystem validation - from initial silicon bring-up through feature enablement, performance tuning, and customer issue resolution.
You will work on LPDDR5/LPDDR5X/DDR5 technologies, enabling high-performance memory systems and ensuring first-pass silicon success across multiple programs.
THE PERSON: You are a hands-on debug engineer who thrives in exciting, challenging bring-up environments and consistently takes end-to-end ownership of problems-from identifying the root cause to driving cross-team resolution. You are equally comfortable debugging waveform-level issues, collaborating closely with firmware and BIOS teams, aligning multiple engineering organizations, and communicating clearly with leadership during critical program phases. You bring a strong sense of ownership, urgency, and accountability, and you are motivated by solving complex system-level problems that directly influence overall product success.
KEY RESPONSIBILITIES: - Own UMC-related post-silicon bring-up, debug, and feature enablement across client and server programs
- Serve as the primary liaison between Validation, Firmware, Design, and SoC teams, acting as a technical bridge across functions
- Drive end-to-end issue ownership by identifying, analyzing, and pushing system-level memory issues to full resolution
- Debug memory subsystem interactions spanning controller, PHY, firmware, and platform components
- Perform deep root-cause analysis using waveforms, lab instrumentation data, logs, and cross-environment correlation
- Translate low-level technical findings into system-level impact, risks, and clear action plans for stakeholders
- Develop and execute validation plans for memory subsystem features, including functional, performance, latency, bandwidth, and power-state behavior
- Track issues through closure using JIRA/debug flows and ensure alignment across teams in fast-paced bring-up environments with shifting priorities
- Provide concise, ongoing status updates, risk assessments, and debug summaries to program leadership
- Support customer-facing issues and escalations with timely technical investigation and resolution
- Contribute to improvements in post-silicon debug methodology, infrastructure, workflows, and cross-team communication
PREFERRED EXPERIENCE: - Strong understanding of DDR memory systems (DDR5 / LPDDR5) and controller/PHY interactions
- Hands-on experience with post-silicon bring-up and validation in a lab environment
- Familiarity with BIOS, firmware flows, and low-level hardware initialization sequences
- Experience debugging power states, clocking, resets, and sequencing behavior
- Knowledge of ECC, RAS, memory reliability features, and system-level performance characteristics
- Background working with SoC-level validation, integration teams, and multi-IP subsystem interactions
- Proficiency with logic analyzers, oscilloscopes, and silicon debug tools
- Experience using Python or similar scripting languages for automation, log parsing, or data analysis
- Demonstrated ability to operate effectively in fast-moving bring-up environments and communicate across engineering disciplines without direct authority
- Experience driving collaborative issue resolution between Design, Firmware, and Validation teams while maintaining clear ownership
ACADEMIC CREDENTIALS: • Bachelor's degree in electrical or computer engineering and relevant experience, or
• Master's or PhD degree in Electrical or Computer Engineering with relevant experience
This role is not eligible for visa sponsorship.#LI-DP1
#LI-HYBRID
Benefits offered are described: AMD benefits at a glance.
