Western Digital Technologies

Senior Technologist, Hardware Development Engineering -

Western Digital Technologies • $176K — $235K *
Roseville, CA 95747In-Person
Telecommunications & Hardware
Less than 5 years of experience
Today
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Job Overview by Ladders

Qualifications

  • 5-7 years of professional hardware engineering experience.
  • Proven management of complex programs throughout their lifecycle: from architecture to production ramp.
  • Hands-on expertise in board/system hardware design and ASIC I/O integration.
  • Experience with high-speed interfaces like 100G/200G Ethernet and PCIe Gen 6.
  • Ability to design and simulate high-speed links while addressing SI/PI/EMI constraints.
  • Demonstrated skills in analog circuit design and EMI/EMC knowledge.
  • Familiar with schematic/layout tools such as Cadence or Altium.

Responsibilities

  • Lead board-level hardware design and ASIC integration efforts.
  • Debug complex hardware issues from silicon to board level in lab settings.
  • Create and execute test plans for hardware validation and debugging.
  • Maintaining and improving partnerships with key component manufacturers.
  • Enforce design constraints through regular cross-functional design reviews.
  • Mentor junior engineers and drive design correctness early in the process.
  • Drive collaboration between silicon, package, and board teams for optimal outcomes.

Benefits

  • Comprehensive medical/dental/vision insurance.
  • Paid vacation and sick leave policies.
  • Tuition reimbursement programs available.
  • Employee stock purchase plan for eligible employees.
  • Flexible spending and health savings accounts provided.
Full Job Description
Job Description

We are seeking an Expert-level Hardware Engineer who is equally strong in board-level hardware design and ASIC interface / integration (I/O, package, power integrity, DFT/test, analog, and signal integrity). This is a hands-on role for a recognized subject matter expertise in delivering complex hardware from concept through production, including deep lab bring-up and root-cause complex issues, able to debug across silicon, package, and board.

Qualifications

REQUIRED
  • Professional hardware engineering experience.
  • Proven ownership of multiple complex programs through the full lifecycle: architecture 12 design 12 build 12 bring-up 12 debug 12 qualification 12 production ramp 12 sustaining.
  • Demonstrated, hands-on experience spanning both:
  • Board/system hardware design (schematic ownership, layout partnership, bring-up, debug, standards compliance, manufacturing support)
  • ASIC I/O and integration (I/O architecture decisions, package/substrate considerations, PI/SI co-design, tape-out support, DFT/test hooks)
  • Cutting-Edge High-Speed Interfaces
  • Hands-on experience integrating and debugging leading-edge Ethernet and PCIe interfaces, including:
  • 100G/200G Ethernet PAM4 transceivers (system/channel design, equalization concepts, BER/PRBS testing, standards compliance planning and test)
  • PCIe Gen 6 (system/channel design, equalization concepts, BER/PRBS testing, standards compliance planning and test)
  • Demonstrated ability to design and simulate high-speed links across die/ASIC package/PCB/connectors/cabling, balancing SI/PI/EMI and manufacturing constraints.
  • FPGA Board Design
  • Proven experience designing complex boards using cutting-edge FPGAs (e.g., high-end families with high-speed transceivers), including:
  • Power architecture and sequencing for FPGA multi-rail systems
  • High-speed transceiver channel design, with associated reference clock design,
  • reset/boot/strap
  • Bring-up and debug using vendor tools, link training, PRBS/IBERT-style testing, and lab correlation
  • Ownership of FPGA-based platform bring-up from first power-on through high-speed link validation and system integration.
  • AMD FPGA Knowledge preferred
  • Board-Level Design
  • Expert schematic design and review for high-complexity boards (compute/networking/accelerator-class or equivalent).
  • Strong experience with:
  • Multi-rail power distribution networks (frequency domain impedance control, sequencing, fault handling)
  • High-speed interfaces (DDR, PCIe, Ethernet/SerDes-based links, USB, I2C, SPI, MIPI-based on product needs)
  • Controlled impedance trace design (understanding manufacturing and cost tradeoffs)
  • Clocking/reset/fault tolerant architectures and debug access design
  • General analog circuit design
  • Proven partnership with layout teams to define and enforce:
  • Stackups, reference planes, return paths, via design and strategy, routing constraints
  • Differential pair controlled impedance routing, channel constraints, connector strategy, manufacturability
  • Signal Integrity (SI) & Power Integrity (PI) Across Die / Package / Board
  • SI design experience: Insertion loss, return loss, eye/jitter concepts, electrical noise abatement, termination, discontinuities, correlation of models to measurements.
  • Deep PI/PDN experience: target impedance approach, decap strategy, anti-resonance mitigation, transient response, measurement and correlation.
  • Practical EMI/EMC grounding/shielding/filtering understanding grounded in design and lab realities.
  • ASIC I/O, Package, and Power Co-Design
  • Ability to own or co-own ASIC I/O choices:
  • I/O standards, voltage domains, ESD strategy, drive/slew tuning, noise coupling/SSO considerations
  • Strong understanding of package/substrate impacts:
  • Pinout/ballout tradeoffs, escape routing constraints, lane swapping realities
  • Package parasitics effects on SI/PI and timing margins
  • Thermal/mechanical considerations influencing reliability and assembly
  • Power architecture competence spanning system and ASIC-aware constraints (noise isolation, domain partitioning, bring-up hooks).
  • DFT / Test Strategy Bridging Silicon 12 Board 12 Manufacturing
  • Strong working knowledge of DFT concepts and productization:
  • JTAG/boundary scan, scan/ATPG fundamentals, BIST/loopbacks/PRBS, on-chip monitors/telemetry
  • Experience defining debug and manufacturing test strategy:
  • Test access, test point strategy, coverage vs SI impact, failure analysis workflows
  • Analog & Mixed-Signal Practical Depth
  • Practical capability to own/review analog subsystems relevant to high-performance designs:
  • Clock generation/distribution and jitter sensitivity
  • Filtering/biasing, stability fundamentals, measurement integrity/noise coupling
  • Mixed-signal partitioning and grounding strategy
  • Hands-On Lab Debug Expectations
  • Expert in structured bring-up and root-cause debug:
  • Creation and execution of EVT test plan
  • High-speed measurement competence (Oscilloscopes, BERT, network analyzers, spectrum analyzers, probing strategy, fixtures, de-embedding awareness)
  • Ability to correlate bench measurements back to simulation and drive corrective actions
  • Tools & Workflow
  • Familiarity with mainstream schematic/layout environments (e.g., Cadence/Altium/Mentor-class tools) and constraint-driven design practices.
  • Comfortable with SI/PI modeling workflows (IBIS/AMI, S-parameters, SPICE-level reasoning) and validation against lab data.
  • Strong documentation, design review, ECO, and risk-management discipline
  • Operates as a cross-functional technical leader across silicon, package, board, validation, test, manufacturing.
  • Writes clear specs/constraints that prevent rework (I/O requirements, channel budgets, PDN targets, bring-up/test access).
  • Drives design reviews that identify real risks early and mentors engineers across experience levels.
  • Drive partnerships with key IP, component and manufacturers.
  • Examples where you personally identified high-speed margin failures (examples: 100/200G PAM4 and/or PCIe Gen 6 or slower data rates) through SI/PI analysis or lab testing.
  • Examples of cross-boundary root cause (ASIC 12 package 12 board) with measurable corrective actions.
  • Examples where you improved observability/DFT/test hooks to accelerate bring-up and production readiness.

PREFERRED
  • Advanced packaging or multi-die systems (e.g., chiplets/interposers/HBM-class integration).
  • Ownership of qualification/compliance (EMC, safety, thermal/mechanical) and production yield improvement.
  • Experience with design for low cost, second-source strategies, and sustained field reliability initiatives.

Salary Range

176,600.00-235,400.00

Compensation & Benefits Details
  • An employee's pay position within the salary range may be based on several factors including but not limited to (1) relevant education; qualifications; certifications; and experience; (2) skills, ability, knowledge of the job; (3) performance, contribution and results; (4) geographic location; (5) shift; (6) internal and external equity; and (7) business and organizational needs.
  • The salary range is what we believe to be the range of possible compensation for this role at the time of this posting. We may ultimately pay more or less than the posted range and this range is only applicable for jobs to be performed in California, Colorado, New York or remote jobs that can be performed in California, Colorado and New York. This range may be modified in the future.
  • If your position is non-exempt, you are eligible for overtime pay pursuant to company policy and applicable laws. You may also be eligible for shift differential pay, depending on the shift to which you are assigned.
  • You will be eligible to be considered for bonuses under either WD's Short Term Incentive Plan (2STI Plan2) or the Sales Incentive Plan (2SIP2) which provides incentive awards based on Company and individual performance, depending on your role and your performance. You may be eligible to participate in our annual Long-Term Incentive (LTI) program, which consists of restricted stock units (RSUs) or cash equivalents, pursuant to the terms of the LTI plan. Please note that not all roles are eligible to participate in the LTI program, and not all roles are eligible for equity under the LTI plan. RSU awards are also available to eligible new hires, subject to WD's Standard Terms and Conditions for Restricted Stock Unit Awards.
  • We offer a comprehensive package of benefits including paid vacation time; paid sick leave; medical/dental/vision insurance; life, accident and disability insurance; tax-advantaged flexible spending and health savings accounts; employee assistance program; other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity; tuition reimbursement; transit; the Applause Program; employee stock purchase plan; and the WD Savings 401(k) Plan.
  • Note: No amount of pay is considered to be wages or compensation until such amount is earned, vested, and determinable. The amount and availability of any bonus, commission, benefits, or any other form of compensation and benefits that are allocable to a particular employee remains in the Company's sole discretion unless and until paid and may be modified at the Company's sole discretion, consistent with the law.

About Western Digital Technologies

Western Technology Investment is a venture capital firm that specializes in offering acquisition financing to revenue-generating firms. The firm provides debt and lease financing to venture capital backed technology companies.

Western Digital Technologies Careers

Join the innovative world of Western Digital Technologies, a leader in data storage solutions, where we are committed to empowering our global team of professionals. This is an unparalleled opportunity to advance your career with a company at the forefront of technological innovation and digital storage.

Work You’ll Do

At Western Digital Technologies, you will be part of a dynamic team that drives data innovation across various industries. Our commitment to excellence and leadership in the technology sector provides a unique platform for professionals to influence the future of digital storage and management solutions.

Explore Job Opportunities and Growth

Western Digital Technologies offers a variety of job opportunities that cater to a range of skills and experiences. Whether you’re looking for an entry-level position or a more senior role, our company is eager to support your professional growth through challenging projects and continuous learning opportunities.

Internship Programs

Kickstart your career with Western Digital Technologies through our internship programs. These positions are designed to give you hands-on experience and insights into our day-to-day operations, preparing you for a full-time role in our company. Interns at Western Digital Technologies gain invaluable industry knowledge, networking opportunities, and professional skills under the guidance of experienced mentors.

Benefits and Culture

We pride ourselves on a culture that fosters diversity, innovation, and leadership. Western Digital Technologies is dedicated to providing employees with a supportive work environment where everyone is encouraged to be their best. Our benefits package is comprehensive, including health, dental, and vision insurance, employee wellness programs, and significant career development opportunities.

Join Our Team

We are continuously hiring creative, curious, and motivated individuals who are ready to drive innovation in the technology space. Explore open positions that match your skills and interests on our careers page. At Western Digital Technologies, we value diversity and are committed to creating an inclusive environment for all employees.

Professional Development and Training

Advance your career with Western Digital Technologies through our professional development programs. We offer a range of training and development options, including leadership training, skills enhancement workshops, and diversity training sessions to help you grow as a leader and innovator in our industry.

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Apply Now

Ready to take the next step in your career? Submit your resume, prepare for your interview, and join a team that’s redefining the future of technology. At Western Digital Technologies, your future is waiting.

SEARCH WESTERN DIGITAL TECHNOLOGIES JOBS

Join us at Western Digital Technologies, where your career growth is integrated with innovation and leadership, empowering you to reach new heights in the technology industry.
Learn more about Western Digital Technologies
Size
65,600 employees
Market Cap
$9.9 billion
Industry
Enterprise Technology
Net Income
$167 million
Founded
1970
5 Year Trend
-0.3%
Revenue
$16.3 billion
NASDAQ
WDC
* Ladders Estimates

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