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X In most instances, this position requires in-person interviews as part of the hiring process.
Minimum qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience with digital design using SystemVerilog RTL.
- Experience with power, performance and area optimizations.
Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience interacting with software, architecture, physical design and other cross-functional teams.
- Knowledge of processor design, accelerators, or memory hierarchies.
About the jobIn this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
You will be part of a team developing cutting-edge ASICs used to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $163000 - $236000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities - Create and own microarchitecture for Compute accelerator IPs.
- Develop implement, and maintain design blocks or components.
- Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
- Work with design verification and validation teams to create testplans to verify, and debug design RTL.
- Work with physical design teams to ensure design meets physical requirements and timing closure.
