In this role, you will work closely with architects, designers, verification engineers, and integration teams to drive execution and delivery of complex IP and subsystem development.
Own end-to-end execution and delivery of IP and subsystem milestones from architecture through release
Define development phases, schedules, milestones, dependencies, and quality expectations with architects and engineering leads
Coordinate execution across architecture, design, verification, validation, software, and SoC integration teams
Identify risks early, drive resolution, and escalate critical issues that threaten execution, quality, or release commitments
Lead technical reviews and execution checkpoints with clear status, actions, and follow-through
Drive alignment on specifications, interfaces, release content, and handoff requirements
Drive priority and trade-off discussions within IP scope
Resolve interface issues, integration dependencies, and execution trade-offs with internal and external stakeholders
Support release readiness, signoff reviews, and integration milestones by driving issues to closure
Improve execution visibility through data collection, milestone tracking, risk registers, and engineering metrics
BSEE required; MSEE preferred with 7+ years of industry related experience
Good understanding of IP development process and methodology with technical depth and project execution leadership
Experience in protocols like AHB/AMBA, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers a plus.
Experience driving execution across multidisciplinary teams, with ownership of plans, schedules, dependencies, risks, and tracking
Strong planning skills and hands-on use of Microsoft Project, Jira, Confluence, Power BI, and Excel for scheduling, tracking, risk management, and data collection
Good understanding of semiconductor development lifecycle, design and verification methods, and integration dependencies
Experience in all aspects of RTL design flow fromSpecification/Micro-architecturedefinition to design and verification, Timing Analysis, DFT and Implementation a plus
Good understanding on Chip Assembly, IP Integration, RTL signoff tools and CDC/RDC/Lint/Synthesis.
Able to work effectively with global teams; self-motivated to solve problems and manage deliverables
Excellent interpersonal and communication skills
Excellent leadership and negotiation skills
