Axiado Corporation

Senior FPGA Design Engineer

Axiado Corporation$120K — $160K *
Technical Services
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • 5-7 years of industrial experience in FPGA design
  • Strong background in RTL design for FPGAs
  • Proficient with FPGA tools like Vivado and Protocompiler
  • Experience with IP integration and CPU interfacing
  • Skilled in RTL simulation testing and software debugging
  • Familiarity with communication protocols such as PCIe and USB
  • BS or MS degree in Electrical Engineering, Computer Engineering, or Computer Science (preferred)

Responsibilities

  • Design RTL for FPGA, including porting and timing closure
  • Set up and test FPGA simulations
  • Perform FPGA system validation and debugging
  • Collaborate with the software team to validate FPGA systems
  • Integrate various IPs into FPGA designs

Benefits

  • Opportunity to work in a leading security management company
  • Access to cutting-edge technology in cloud and 5G sectors
  • Collaborative environment with emphasis on problem-solving and mutual support
  • Focus on continuous learning and professional development
  • Located in Silicon Valley, a hub for technology and innovation
Full Job Description
Job Description

Senior FPGA Design Engineer position is your opportunity to join one of the industry's leading companies in platform security management and ransomware detection for cloud datacenters, 5G infrastructure and disaggregated compute ecosystems. You should have prior knowledge about RTL design, FPGA prototyping and computer architecture. As the Senior FPGA Design Engineer for Axiado, you will have the opportunity to work in design, verification, debug and system integration. You will work closely with the Architecture, Verification, ASIC Design and Software teams, and report into the Engineering organization.

Key Responsibilities
  • RTL design for FPGA, including RTL porting, IP integration, closing timing and generating bit streams
  • FPGA simulation setup and testing
  • FPGA system setup, validation and debug
  • Work with SW team to bringup and validate FPGA system product


Qualifications
  • Product experience with FPGAs and related tools such as Vivado and Protocompiler
  • Strong experience in RTL design, especially design for FPGAs
  • Integration of IPs and CPUs for FPGA
  • Experience in RTL simulation testing
  • Experience in bringing up and debugging SW on FPGA systems
  • Familiarity with PCIe, USB, Ethernet, SPI. The following are pluses: ESPI, SGPIO, LTPI
  • Self-driven, good problem solving and communication skills
  • BS or MS (preferred) degree in EE/EECS/CS or equivalent.
  • At least 5 years of industrial experience


Additional Information

Axiado is committed to attracting, developing, and retaining the highest caliber talent in a diverse and multifaceted environment. We are headquartered in the heart of Silicon Valley, with access to the world's leading research, technology and talent.

We are building an exceptional team to secure every node on the internet. For us, solving real-world problems takes precedence over purely theoretical problems. As a result, we prefer individuals with persistence, intelligence and high curiosity over pedigree alone. Working hard and smart, continuous learning and mutual support are all part of who we are.

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