Please Note:To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.
Samsung Semiconductor Inc is looking for a talented Senior/Staff PLL Designer with strong background and hands-on experience in PLL and clock generation circuit design. The candidate will work on the design and development of high-performance PLL and clocking subsystems for RF transceivers, SerDes, and high-speed I/O applications in advanced deep-submicron CMOS technologies.
What You'll Do- Design PLLs and clock generation circuits (integer-N, fractional-N, digital PLLs, clock multipliers/dividers) for RF and SerDes applications
- Design critical PLL building blocks including VCO/DCO, charge pumps, loop filters, phase/frequency detectors, dividers, and phase interpolators
- Perform PLL system-level modeling, noise analysis, and jitter budgeting using Matlab/Simulink
- Drive design verification including transistor-level simulation, Monte Carlo analysis, and silicon correlation
- Collaborate with digital, layout, and systems teams to deliver PLL IPs meeting performance, power, and area targets
- Support bring-up, characterization, and debug of silicon prototypes in the lab
What You Bring- Bachelor's with 5+ years of experience or Master's with 3+ years of experiences or PhD with 0 years of experience in a related field.
- Extensive hands-on experience designing PLLs in deep sub-micron CMOS (5nm-28nm), including at least one of: integer-N, fractional-N, digital PLL, or sub-sampling PLL topologies
- Deep understanding of PLL system theory: phase noise, jitter, loop dynamics, reference spurs, and fractional spurs
- Proficiency in IC design CAD tools such as Spectre, SpectreRF, and AMS simulator
- Strong Matlab/Simulink skills for behavioral modeling and system-level analysis
- Familiarity with Verilog/SystemVerilog for mixed-signal simulation
- Solid understanding of layout-sensitive design and ability to guide critical PLL layout (LC tank, charge pump, reference path)
- Lab characterization experience: phase noise measurement, jitter analysis, and spectrum analysis equipment
- Experience with RTL design (Verilog/SystemVerilog) to implement PLL-related digital calibration circuits, including frequency calibration, phase calibration, and background self-calibration logic
- Excellent problem-solving, analytical, and communication skills
What We OfferThe pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job-related knowledge, skills, and experience. We also offer incentive opportunities that reward employees based on individual and company performance.
This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.
Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.
Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.
Care for Family Whatever family means to you, we want to support you along the way-including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.
Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.
Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.
Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you.
Base Pay Range
$138,000-$206,000 USD
