The
Senior Engineer - HBM Design for Test (DFT) is an experienced technical contributor responsible for the
definition, implementation, integration, and support of DFT solutions across HBM core die and base die for current and next-generation HBM products.
This role focuses on
driving defined DFT architectures, contributing to DFT specifications, and partnering with multi-functional teams to ensure DFT features meet test, quality, and manufacturability requirements. The Senior Engineer works closely with DFT Architecture, Design Engineering, Product Engineering, Test, and DFT Verification to support successful tape-out, silicon bring-up, and qualification.
Key Responsibilities- Implement and integrate DFT features for assigned HBM core die and base die designs in alignment with established DFT architecture and guidelines
- Contribute to the development, review, and maintenance of DFT specifications, requirements, and implementation guidelines
- Ensure DFT implementations support high-quality, efficient, and manufacturable HBM products
- Collaborate with Design Engineering, Product Engineering, Test, and DFT Verification to:
- Translate manufacturing and test requirements into actionable DFT implementations
- Support alignment between DFT specifications and verification coverage
- Identify, debug, and resolve DFT-related issues during build execution, tape-out, and silicon bring-up
- Serve as a DFT contributor or sub-domain owner for assigned programs or functional areas
- Support reuse and standardization of DFT logic and methodologies across HBM products under mentorship from DFT architecture leadership
- Participate in design, verification, and readiness reviews, providing technical guidance and issue resolution support
- Document DFT implementations, lessons learned, and procedures to support organizational knowledge exchange
- Using AI to improve job functions
Minimum Qualifications- Bachelor's degree in Electrical Engineering or related field (Master's preferred)
- 5+ years of experience in semiconductor development with exposure to DFT, design, verification, test, or silicon debug
- 1+ years of experience in memory architectures (HBM or DRAM preferred)
- 1+ years of experience implementing DFT features and supporting DFT-related debug and bring-up activities
Preferred Qualifications- Experience working with DFT verification teams and coverage methodologies
- Familiarity with manufacturing test flows and test requirements for advanced memory products
- Strong written and verbal communication skills
- Ability to work effectively in a multi-functional, program-driven environment
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
AI alert
: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
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