Job Title: Senior Engineer

Job Descriptions: Responsible for the Design Rule Check, Layout vs. Schematic checking and fixing all PDV/EMIR/Noise/SigEM violations and errors. You may also do customization and implementation of top clocks and implement timing ECOs on high performance blocks. Specific job duties include: DRC/LVS/ERC/ANTENNA analysis and clean up, Floorplan analysis and congestion solution; Power IR/EM analysis and fix; Signal EM/Noise analysis and fix; Physical verification sign off; Implement ECOs for timing closure; Customized Clock tree structure; May also perform floorplan, place and route.

Requirements: Master's degree or foreign equivalent in Electrical Engineering, Computer Engineering, or a related field of study, and one (1) year of experience in a related position.

Work experience or academic coursework must have included: Knowledge of hardware design courses including VLSI design, digital integrated circuits, logic design, design for testing, computer architecture, and digital design automation; Knowledge of major EDA tools/design flows; Experience with physical implementation or design verification; Experience in Perl/TCL language programming; Experience in N16 and below technology, Chip level integration, and wire editing, low-power implementation methodology; Experience with Netlist-GDS P&R, signoff task; and Experience in block level implementation or chip integration and signoff.

Work site: TSMC Technology Inc., 2851 Junction Ave., San Jose, CA 95134 and various unanticipated work locations

Salary Range: $155,896 to $167,000/year.

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Date: Aug 13, 2026

Country/Region: US

City: San Jose

Company: TSMC Technology, Inc.