Qualifications

• 4+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs
• Strong understanding of DFT fundamentals including controllability and observability
• Proven expertise in ATPG pattern generation and analysis
• Experience with MBIST architectures and memory diagnostics
• Knowledge of IO Test methodologies for validation
• Solid understanding of clock DFT and clock verification
• Familiarity with industry-standard DFT/ATPG EDA tools
• Analytical, problem-solving, and communication skills

Responsibilities

• Architect, implement, and validate DFT solutions for GPU/SoC designs
• Lead scan-based DFT implementation and test logic integration
• Develop and debug ATPG patterns for various fault models
• Implement MBIST architectures for memory testing
• Plan and validate IO Test for reliable interfaces
• Support clock DFT activities and at-speed test enablement
• Analyze fault coverage reports and drive improvements
• Collaborate with RTL, physical design, and product engineering teams

Benefits

• Provide robust DFT solutions for high-performance GPUs and SoCs
• Work in a fast-paced, high-performance semiconductor environment
• Opportunity to collaborate with cross-functional teams
• Be part of a company focused on silicon reliability and quality
• Engage in advanced test features like MBIST and IO Test