About the roleWe are seeking an experienced to own the end-to-end testing, characterization, and failure analysis strategy for complex, next-generation multi-die packages.
You will own the complete validation lifecycle across a multi-die architecture-covering high-speed die-to-die (UCIe) interconnects, Power Delivery Networks (PDN/PMIC), Platform Management Controllers (PMC), PCIe/CXL subsystems.
Additionally, you will apply statistical analysis and machine learning to test data-driving outlier detection, bench-to-ATE correlation, and predictive telemetry signals-without treating ML models as a substitute for true physical root-cause analysis.
What you'll doTest content and automation- Test Plan Ownership: Define development test strategies, coverage targets, content architecture, and strict traceability from architectural requirements to validation evidence.
- Bare-Metal & C/Python Test Content: Write low-level C and Python test suites-including bare-metal exercisers, traffic generators, stress patterns, and custom firmware drivers/hooks.
- Scalable Automation & HIL: Build robust test frameworks featuring instrument control, automated sequencing, structured result capture, and Hardware-in-the-Loop (HIL) CI/CD integration for continuous validation.
- Bench-to-ATE Handoff: Develop lab-to-ATE correlation test suites and drive smooth handoffs to Product & Test Engineering (PTE)
- Own the development test plan: coverage goals, content architecture, and the traceability between a requirement, the test that exercises it, and the evidence it passed.
Characterization and margin- Injection Frameworks: Build minimally invasive fault-injection hardware/software infrastructure that perturbs target datapaths without destabilizing the test setup itself.
- Protocol & Platform Fault Testing: Execute rigorous error campaigns targeting CRC retries, lane degradation/repair, sideband timeouts, PCIe AER, DMA/IOMMU translation faults, and PMIC reset conditions.
- Firmware & Resilience Testing: Validate system firmware error handlers, watchdog timers, and hardware-level fault containment behavior under out-of-spec conditions.
Required qualifications- Experience: 8-10+ years in post-silicon validation, system software testing, silicon bring-up, or development test for complex SoCs / ASICs / GPUs.
- Software/Firmware Skills: Advanced proficiency in C and Python for low-level bare-metal test content, hardware abstraction, and automation frameworks.
- Silicon Characterization: Proven experience with Shmoo plotting PVT corner testing, jitter/margin analysis, and guard-band definition.
- Fault Injection Expertise: Hands-on experience building or executing error-injection and recovery validation campaigns on production silicon.
- Lab Instrumentation: Fluency with oscilloscopes, protocol analyzers (PCIe/CXL), logic analyzers, BERTs, thermal chambers, controllable power supplies, and JTAG debuggers.
- High-Speed & System Protocols: Practical, protocol-level understanding of high-speed serial interfaces (PCIe, CXL, or UCIe) and control buses (I2C, SPI, UART, PMBus, SMBus).
- Power Systems: Solid grasp of system power delivery-including sequencing, PMIC telemetry, DVFS, voltage regulation, and protection trip limits.
- Data & Tooling: Competency with toolchains (Git, CMake, GCC/Clang, CI pipelines) and statistics/data analysis over test populations.
- Education: BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
- AI Tool usage : AI coding and automation tool is must for this role
CompensationThe compensation range shown below represents total target cash compensation and includes both base salary and target bonus. Actual compensation will vary based on factors such as experience, skills, qualifications, job level, and work location.
In addition to cash compensation, this position is eligible for equity in the form of stock options, giving you the opportunity to share in the Company's long-term growth and success.
The pay range for this role is:
180,000 - 216,000 USD per year (US)
