Job Details:Job Description:About the RoleAs a
Sr. Debug Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable effective verification. Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan. Using system full application to verify performance and identify short falls.
Key Responsibilities:- Pre-silicon system verification. This include SoC, FPGA & Full Chip design verification.
- Create testcase and testbench with UVM methodology
- Fullchip/system functional verification, by defining verification strategies/methodology and test plan to enable effective verification
- Experience with Design for Debug (JTAG, High speed USB, PCIe based debug, Visualization of Internal Signal) architecture and design verification of same.
- Experience with ARM and RISC Debug Architectures is desired with focus on design verification.
- Any prior working experience on UltraSoC/ Tessent Embedded Analytics Debug Architecture will be a plus but not must for this position.
- Coordinate/interface cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan
- Experience on Emulation will be an add on.
Salary RangeThe pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$149,100 - $215,000 USDWe use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
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Qualifications:Minimum Qualifications- 8+ years of experience with complex ASIC designs and/or verification
- 8+ years of experience with SystemVerilog language
- 8+ years of experience on UVM verification methodology, and formal verification method
- 8+ years of experience scripting in Linux/ Unix environments as well as proficiency in Perl and or Python is desirable.
- Strong communication skills and the ability to work with a team spread across different geography sites
Job Type: Regular
Shift:Shift 1 (United States of America)
Primary Location:San Jose, California, United States
Additional Locations: 
