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X In most instances, this position requires in-person interviews as part of the hiring process.Note: By applying to this position you will have an opportunity to share your preferred working location from the following:
Mountain View, CA, USA; Austin, TX, USA; Portland, OR, USA; Poughkeepsie, NY, USA.
Minimum qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 10 years of experience in microprocessor architecture, microarchitecture, performance and design.
- Experience with CPU architecture with CPU blocks, along with performance modeling, analysis, correlation, and workload characterization.
- Experience with processor instruction set architecture (e.g., ARM, RISC-V, x86) and system software components, such as Linux, drivers, and runtime.
Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience in performance modeling, debugging, and demonstrating the benefits of new ideas.
- Knowledge of processor instruction set architecture (e.g., ARM, RISC-V, x86).
- Ability to generate innovative microarchitectural ideas to improve performance in actual silicon.
- Strong critical thinking, communication, and advocacy skills.
About the jobIndividual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $278000 (USD) 20% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities - Deliver solutions to complex problems that may be ambiguous and/or lacking clear precedent. These problems include CPU performance, microarchitecture design, tool infrastructure, methodology, and so on.
- Plan, drive, and evaluate ARM's architecture features from both architecture and performance angles.
- Define and write CPU subsystem architecture specifications.
- Lead the collaboration with RTL, design verification, and physical design teams to develop a high performance and efficient CPU implementation.
- Drive performance correlation between the performance model and RTL implementation and perform pre-silicon and post-silicon performance bug triage.
