Minimum qualifications:- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience in ASIC design, design automation, or a related field.
- Experience programming in Python and shell scripting, and experience with SystemVerilog or other hardware description languages.
- Experience with EDA tools and typical ASIC design and verification flows.
- Experience with version control systems (e.g., Git, Perforce) and with build systems (e.g., Bazel, Make).
- Experience with continuous integration systems (e.g., Jenkins).
Preferred qualifications:- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with data visualization tools and dashboard creation.
- Understanding of digital design principles.
- Proven ability to work independently on end-to-end tasks and projects.
- Strong communication and collaboration skills, with the ability to work effectively in a team environment.
- Excellent problem-solving and debugging skills.
About the jobIn this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
The US base salary range for this full-time position is $138,000-$198,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities - Own Compute IP releases to the SoC. Enhance scripts and flows for SoC releases to reduce manual effort and cycle time for IP releases.
- Use Python to improve efficiency and quality in top-level IP assembly, focusing on connectivity and configuration.
- Automate IP versioning and integration for cross-project consistency.
- Liaise between Design and Physical Design teams to refine automation for reliable, high-quality branch handoffs. Partner with multi-functional teams to deploy automation for development pain points and document methodologies
- Maintain automated systems to validate tool flows and design health.
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