Cadence Design Systems

Product Engineer II (EMIR / PDN Analysis & Power Integrity)

Cadence Design Systems$101K — $188K *
Information Technology
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's Degree in Electrical/VLSI Engineering with 3+ years of experience or a Master's degree in a related field.
  • Knowledge of advanced digital logic and VLSI design principles.
  • Experience in power IR drop analysis and circuit design.
  • Familiarity with automatic placement and routing tools.
  • Proficiency in Python or TCL scripting.

Responsibilities

  • Collaborate within the product engineering team on Power Noise Reliability analysis.
  • Develop expertise in emerging methodologies like AI-driven IR mitigation.
  • Partner with R&D for the advancement of optimization methods.
  • Provide support to strategic customers in the Multiphysics domain.
  • Drive solutions in collaboration with functional product engineering.

Benefits

  • Paid vacation and holidays.
  • 401(k) plan with employer matching.
  • Employee stock purchase plan.
  • Variety of medical, dental, and vision plan options.
Full Job Description
Job Responsibilities • Be part of the product engineering team working on Power Noise Reliability analysis platform within Digital Sign-off Group at Cadence. • Build domain expertise in power integrity , 3DIC analysis & optimization , Industry's first AI driven IR mitigation & fixing methodology , electrothermal optimization for digital designs. • Work closely with R&D to facilitate the development of these methodologies and flows. • Responsibilities also including supporting strategic customers and functional product engineering driving solutions in the Multiphysics space. Minimum Qualifications • Bachelor's Degree in; Electrical / VLSI Engineering with 3+ years related experience • OR Masters with relevant courses in digital systems in Electrical Engineering Experience and Technical Skills required • Coursework related to advanced digital logic design and advanced Very Large Scale Integrated-circuit (VLSI) • Fundamental understanding in Digital logic Design, CMOS logic Design, Power IR drop analysis, Circuit Design and Analysis, Digital and Behavioral simulations • Relevant coursework/projects or experience in physical design implementation flow using automatic placement and routing tool. • Ability to debug IR drop, Timing, and Electrical PDN issues in relation to IR and EM is a plus • Knowledge on Python or TCL scripting. Behavioral skills required • Must possess strong written, verbal and presentation skills. • Ability to establish a close working relationship with both customer peers and management. • Explore what's possible to get the job done, including creative use of unconventional solutions. • Work effectively across functions and geographies. • Push to raise the bar while always operating with integrity. The annual salary range for California is $101,500 to $188,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

About Cadence Design Systems

Cadence Design Systems, Inc. is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
Learn more about Cadence Design Systems
Size
9,300 employees
Market Cap
$43.9 billion
Industry
Net Income
$590.6 million
Founded
2018
5 Year Trend
+10.5%
Revenue
$2.6 billion
NASDAQ

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