Principal RTL Methodology Architect, Austin, Texas

On-Site, Hybrid work schedule.

This is not a remote work opportunity.

ASIC / SoC Architecture | RTL Design Methodology | IP Reuse Platforms | RTL Quality Signoff

What You'll Do
Principal-level Silicon Frontend Architect with deep expertise in RTL design methodology, reusable IP architectures, and RTL quality signoff frameworks for large-scale ASIC and SoC development.
Extensive experience defining scalable frontend design methodologies used across global engineering organizations to improve RTL quality, reuse, and development efficiency.
Combines methodology leadership with hands-on RTL execution, actively contributing to RTL microarchitecture and design implementation while developing flows and infrastructure that enable high-quality silicon delivery.
Proven ability to drive lint-first RTL development, IP reuse strategies, and automated frontend quality frameworks using industry tools such as SpyGlass and VC-based static analysis flows.

What You'll Bring
Strong interest in Artificial Intelligence and its transformative impact on silicon design, with a focus on applying AI/ML techniques to:
• enhance RTL design productivity and code generation
• enable intelligent linting and static analysis
• optimize design space exploration and microarchitecture decisions
• improve automation of frontend design and verification workflows
Actively exploring how AI-driven methodologies can redefine traditional silicon development flows, enabling higher design efficiency, faster convergence, and improved silicon quality at scale.
Key Qualifications:
• Deep expertise in SystemVerilog/Verilog RTL design, microarchitecture definition, and implementation for complex ASIC and SoC designs.
• Strong experience in high-performance block design, subsystem integration, and scalable RTL architecture across IP and SoC levels.
• Proven leadership in defining and deploying enterprise-scale RTL design methodologies and frontend CAD architectures.
• Expert in lint-first RTL development methodologies using SpyGlass and Synopsys VC SpyGlass / VC Lint for RTL quality signoff.
• Extensive knowledge of structural RTL validation, CDC analysis, and static quality gates for pre-silicon design signoff.
• Strong background in IP reuse architecture, including reusable RTL frameworks, standardized interfaces, and multi-program reuse strategies.
• Experience in low-power RTL design methodologies, including UPF-aware design, power domains, isolation, and retention strategies.
• Proficiency in frontend EDA tools including RTL simulators (VCS, Xcelium, Questa), linting, CDC, and synthesis integration flows.
• Strong expertise in automation and infrastructure development using Python, scripting, CI/CD pipelines, and design quality dashboards.
• Strong interest in AI-driven silicon design methodologies, with focus on applying AI/ML to improve RTL design productivity, intelligent linting, design space exploration, and next-generation frontend automation.

What You'll Own

What You'll Own
• Lead architecture, development, and deployment of RTL design methodologies and frontend design flows across IP, subsystem, and SoC programs.
• Define and enforce RTL quality signoff frameworks, including lint, CDC, and static analysis integrated into CI-driven development flows.
• Drive lint-first design adoption and establish standardized RTL coding guidelines and quality metrics across engineering teams.
• Architect and scale reusable IP platforms and configurable RTL frameworks to enable efficient multi-program silicon development.
• Develop and optimize frontend design flows integrating static analysis, simulation, and synthesis readiness checks.
• Maintain ~50% hands-on RTL design involvement, contributing to microarchitecture development and critical silicon blocks.
• Build and deploy automation frameworks and CI/CD pipelines to improve design productivity, regression efficiency, and quality tracking.
• Collaborate cross-functionally with design, CAD, verification, and physical implementation teams to optimize frontend workflows and silicon readiness.
• Identify methodology gaps and drive continuous improvement in design processes, tools, and infrastructure, including exploration of AI-assisted design techniques.
• Drive innovation in AI-enabled RTL design and frontend methodologies, evaluating opportunities for machine learning to enhance design quality, automation, and development efficiency.

Education & Experience
• BS/MS, Electrical Engineering, Computer Science or similar with 10+ years of experience.

What happens once you apply?
Click Here to find all you need to know about what our typical hiring process looks like.

DISCLAIMER: The above statements are intended to describe the general nature and level of work being performed by employees in this position. They are not an exhaustive list of all responsibilities, duties and skills required for this position, and you may be required to perform additional job tasks as assigned.

Primary country and city: USA Austin, Texas

Job details: Developer

Primary Recruiter: Jim Everett

Compensation and Benefits at Ericsson
At Ericsson, we know that our people are the key to our success. We offer a competitive package to help with your individual needs and goals.

Your Pay
The salary range for this position is dependent on various factors including, but not limited to, location, and the candidate's combination of job-related knowledge, qualifications, skills, education, training, and experience.

Your Health
Ericsson offers excellent health benefits including the choice of three medical plan options and a dental plan option that allow an employee to select the level of coverage that suits their needs. Employees will receive company credits in an amount equal to the cost that Ericsson pays toward the cost of their medical and dental premiums for themselves and eligible covered dependents.

Your Financial Security

We invest in both your short and long-term financial wellbeing. The Ericsson US 401(k) Plan offers an automatic 3% company contribution and Ericsson match $1 for every $1 you put into the 401(k) Plan on the first 3% of your eligible pay, plus 50 cents on every $1 on the next 2% of eligible pay. When you contribute at least 5% of eligible pay, you are receiving Ericsson's full matching contributions of 4%. Matching and company automatic contributions stop when your total eligible pay for the year reaches the IRS limits. Employees will also receive company credits in an amount equal to the cost of basic life insurance and basic accidental death and dismemberment coverage, as well as short-term and long-term disability coverage. Employees also have the option to participate in Ericsson's Stock Purchase Plan.

Your Time
Your work-life balance is important to us. New employees are provided a minimum of 15 days of accrued vacation, up to 3 personal days per year, 11 annual holidays, 8 hours of volunteer time, and 80 hours of sick time annually. Please note paid time off is pro-rated based on the employee's start date. Furthermore, Ericsson provides up to 16 weeks of paid maternity leave and 6 weeks of parental or adoption leave at 100% of pay.

Additional Benefits
Ericsson offers many other company-paid benefits such as financial wellness programs, educational assistance, matching gifts, and recognition programs.