Principal Product Engineer

Celero Communications, Inc.

$150K — $250K *
Telecommunications & Hardware
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's degree in electrical engineering; Master's preferred.
  • 10+ years in product engineering or related IC lifecycle roles.
  • Experience with complex ICs from silicon to volume manufacturing.
  • Strong background in reliability qualification and stress testing.
  • Familiarity with wafer-level test and Known Good Die (KGD) processes.

Responsibilities

  • Drive end-to-end NPI from first silicon to full production.
  • Define NPI milestones and exit conditions across various disciplines.
  • Collaborate with design and operations teams for successful product launches.
  • Execute reliability and qualification strategies for coherent DSP ICs.
  • Define internal product quality targets aligned with market needs.
  • Lead technical engagement with foundry and OSAT partners.
  • Manage yield optimization throughout the manufacturing process.

Benefits

  • Opportunity to work in a growing semiconductor startup.
  • Direct involvement in product success from development to manufacturing.
  • Collaborative environment with engineering and operations teams.
  • Focus on high-performance optical networking technology.
Full Job Description
Principal Product Engineer

About the Job
Celero Communications is building nextgeneration coherent DSP integrated circuits for highperformance optical networking. We are seeking a handson, technically deep Principal Product Engineer to drive the transition of Celero's products from development into qualified, highyield, highvolume manufacturing.

This is a groundfloor opportunity to work directly within Celero's engineering and operations teams, playing a critical role in product success while helping establish the operational foundation of a growing semiconductor company. You will define and execute the productization strategy across New Product Introduction (NPI), reliability, test, quality, and manufacturing ramp for advanced coherent DSP ICs delivered as Known Good Die (KGD) and packaged products.

What you Will Do:
New Product Introduction (NPI)
• Drive endtoend NPI execution from first silicon through qualification, sampling, and volume production.
• Define NPI milestones, readiness criteria, and exit conditions across design, test, reliability, manufacturing, and operations.
• Work closely with silicon design, DFT, test engineering, supply chain, and operations to ensure manufacturable, testable product launches.
• Identify technical and operational risks early and lead mitigation efforts through datadriven decision making.

Reliability & Qualification
• Define and execute reliability and qualification strategies for advancednode coherent DSP ICs, including Known Good Die (KGD) qualification.
• Develop and own reliability stress plans (HTOL, HTSL, temperature cycling, ESD, latchup, earlylife failure, etc.)
• Manage external reliability lab execution, including coverage definition, scheduling, reporting, and failure analysis.
• Analyze qualification data and drive product release readiness based on measured risk and maturity.

Product Quality
• Define internal product quality targets aligned with application and market requirements.
• Own quality metrics related to silicon maturity, yield stability, and manufacturing readiness.
• Drive rootcause analysis for quality or reliability excursions and lead corrective actions.
• Support customer quality discussions as needed, primarily through preparation of data and technical analysis.

Test, Sampling & Production Ramp
• Lead technical engagement with foundry and OSAT partners from wafer fabrication through backend processing and shipment.
• Define and refine production test strategies with test engineering, balancing coverage, cost, yield, and guardbanding.
• Drive engineering builds, characterization lots, and production ramps.
• Ensuring robust handoff from engineering tests flows to stable production manufacturing.

Yield Optimization & HighVolume Manufacturing
• Own yield learning and yield optimization from early silicon through highvolume manufacturing
• Perform deep analysis of wafer sort, die sort, and final test data to identify yield limiters.
• Drive crossfunctional corrective actions across design, process, test, and manufacturing.
• Establish yield targets, dashboards, and regular yield reviews to support sustained volume production.

What you Will Bring:
• Bachelor's degree in electrical engineering or related fields. Master's degree preferred.
• 10+ years of experience in product engineering, silicon manufacturing, reliability engineering, or related IC lifecycle roles.
• Proven experience taking complex ICs from first silicon through qualification and volume manufacturing.
• Strong background in reliability qualification, stress testing, and failure analysis
• Experience with waferlevel test, Known Good Die (KGD), and production test flows.
• Demonstrated success driving yield learning and yield improvement.
• Strong analytical skills and comfort working directly with large manufacturing and test data sets.
• Excellent crossfunctional collaboration skills with a bias toward technical execution

Annual Base Salary Range: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)

Javier Leon
Talent Acquisition

[email protected]
www.celero.inc

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