Principal Engineer, Silicon ValidationLocation: San Jose (on-site)
In this role, you will lead the silicon validation of our optical chiplets. You will define and drive the validation strategy from initial silicon power-on through block and chip level signoff. This is a rare opportunity to apply deep expertise in high-speed SerDes, photonic systems, and post-silicon validation to shape the future of optical interconnect for next-generation AI infrastructure.
Essential Functions:- Lead Validation Strategy: Define and implement comprehensive validation methodologies for our electronic-photonic SoCs, covering initial bringup, functional validation, electrical characterization, and system-level testing. Develop detailed test plans, success criteria, and select appropriate test equipment and methodologies.
- Drive Silicon Bring-up: Lead first silicon power-on and bringup for new tape-outs, collaborating with firmware and design teams to establish operating conditions and validate core functionality from day one.
- Own Block and System Validation: Execute rigorous post-silicon validation of SerDes interfaces, optical control loops, and mixed-signal blocks using industry-standard lab equipment (BERT, DCA, oscilloscopes, OSA, VNA).
- Apply Standards and Best Practices: Draw on industry standards (IEEE, OIF, JEDEC, Ethernet/Optical MSA specs) and semiconductor validation best practices to establish rigorous validation targets, coverage objectives, and signoff criteria.
- Root Cause and Debug: Investigate and drive to closure all silicon failure modes, from signal integrity issues to mixed-signal anomalies, using systematic debug methodologies and close collaboration with design and firmware teams.
- Mentor and Lead: Provide technical leadership and mentorship to senior and junior validation engineers; guide the team's technical execution.
- Deliver High Quality Documentation: Create and maintain comprehensive validation reports, signoff packages, and product performance documentation.
Required Qualifications:- Bachelor's degree in Electrical Engineering or related field with 10+ years of relevant industry experience, or Master's degree with 7+ years of experience.
- Demonstrated leadership in post-silicon validation for complex SoCs or multi-chip packages, including first silicon bringup and full signoff.
- Hands-on expertise with high-speed SerDes validation and characterization (NRZ and PAM-4) using equipment such as BERTs, oscilloscopes/DCAs, and network analyzers.
- Strong proficiency in Python for lab automation, data analysis, and test infrastructure development.
- Experience developing and owning validation test plans end-to-end.
- Deep understanding of communication protocols and standards (Ethernet, PCIe, etc.).
- Excellent communication skills and ability to drive cross-functional technical alignment.
Preferred Qualifications:- MSEE or equivalent
- Familiarity with optical transceiver standards and co-packaged optics integration challenges.
- Knowledge of high-speed standards: Ethernet (200G/400G/800G), PCIe Gen5/6, OIF CEI.
- Experience driving NPI and transition from lab validation to manufacturing test.
Salary Range: $200,000 - $255,000
NOTE TO RECRUITERS:
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don't send candidates to Ayar Labs, and do not contact our managers.
