Application close date:

Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide.

We are seeking a Principal or Sr. Principal IC Design Engineer with extensive hands-on experience in the design of high-speed data converters in advanced FinFET technology nodes. You will be responsible for leading the development of ADCs and DACs and for delivering state-of-the-art performance circuits while contributing to innovative solutions that drive Blue Origin's mission of enabling millions to live and work in space for the benefit of Earth.

Special Mentions:

- Relocation provided

- Travel expected up to 10% of the time

- Interviews will include a technical assessment

- This role will be based onsite in San Diego (preferred), CA; the Bay Area, CA; or Renton, WA. A temporary remote work exception is approved while our Bay Area and San Diego sites are being developed.

Responsibilities include but are not limited to:

• Lead the architecture, development and integration of advanced high-speed data converters (ADCs and DACs), as well as other fundamental analog/mixed-signal functions in advanced FinFET CMOS technologies, focusing on performance optimization, power and trade-off analysis.
• Develop high-level behavioral models inMATLAB, Simulink, orSystemVerilog-AMSto validate system performance before circuit implementation.
• Utilize full proficiency in Spectre and AMS flows to develop high-performance mixed-signal circuits and systems.
• Collaborate with system architects to define block-level performance and interface requirements based on system specifications, ensuring seamless integration into RF payloads and terminals.
• Oversee layout, top-level integration, floorplanning, and verification of the overall design for successful tape-out cycle.
• Work closely with validation and product engineers to develop test plans, facilitate bring-up, optimize performance, and ensure reliable & high-yield production cycles.
• Investigate and implement fundamental analog building blocks to enhance overall circuit performance and mentor junior engineers for best design practices in analog domain.
  

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, or related technical discipline
• Proficiency in the design of high-speed ADCs and/or DACs in FinFET technologies.
• Proficiency in the design of SerDes for high-speed data converters such as DACs.
• Familiarity with analog-to-digital conversion architectures and techniques such as SAR, pipeline, TDC, delta-sigma, interleaved sampling, RF, and sub-sampling.
• Understanding of digital calibration algorithms for impairments of said architectures and techniques.
• Proficiency in mixed-mode and analog/RF modeling, simulation, and verification methodologies using toolsets such as MATLAB, Spectre, SystemVerilog, and AMS.
• Deep understanding of Electromigration and layout-dependent effects on circuit performance, namely in advanced FinFET technologies.
• Extensive experience in silicon characterization and debugging.
• Strong background in fundamental analog/RF building blocks, including amplifiers, filters, oscillators, reference generation and LDOs.
• Chip lead experience.
• Strong communication skills.
• Must be a U.S. citizen or national, U.S. permanent resident (current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
  

Preferred Qualifications:

• MS or PhD in Electrical Engineering with 15+ years of relevant experience.
• Familiarity with RF design concepts and metrics such as noise figure, intercept points, line-up analysis, etc.
• Mixed-signal architecture.
• Fundamental understanding of device physics for process selection and performance optimization.
• Familiarity with chip-level ESD protection design and verification.
• Familiarity with digital design, digital verification, and SystemVerilog modeling.

Base Pay Range for:

Other site ranges may differ

Culture Statement

Dont meet all desired requirements? Studies have shown that some people are less likely to apply to jobs unless they meet every single desired qualification. At Blue Origin, we are dedicated to building an authentic workplace, so if youre excited about this role but your past experience doesnt align perfectly with every desired qualification in the job description, we encourage you to apply anyway. You may be just the right candidate for this or other roles.