Minimum qualifications:- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 5 years of experience in computer architecture, chip architecture, IP architecture, co-design, performance analysis, or hardware design.
- Experience in developing software systems in C or Python.
Preferred qualifications:- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on Computer Architecture, or a related field.
- 8 years of experience in computer architecture, chip architecture, IP architecture, co-design, performance analysis, or hardware design.
- Experience in processor design or accelerator designs and mapping ML models to hardware architectures.
- Experience with deep learning frameworks including TensorFlow and PyTorch.
- Knowledge of Machine Learning market, technological and business trends, software ecosystem, and emerging applications.
- Knowledge of hardware/software stack for deep learning accelerators.
About the jobIn this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will be at the forefront of advancing ML accelerator performance and efficiency, employing a approach that spans compiler interactions, system modeling, power architecture, and host system integration. You will prototype new hardware features, such as instruction extensions and memory layouts, by leveraging existing compiler and runtime stacks, and develop transaction-level models for early performance estimation and workload simulation. A critical part of your work will be to optimize the accelerator design for maximum performance under strict power and thermal constraints this includes evaluating novel power technologies and collaborating on thermal design. You will streamline host-accelerator interactions, minimize data transfer overheads, ensure seamless software integration across different operational modes like training and inference, and devise strategies to enhance overall ML hardware utilization. To achieve these goals, you will collaborate closely with specialized teams, including XLA (Accelerated Linear Algebra) compiler, Platforms performance, package, and system design to transition innovations to production and maintain a unified approach to modeling and system optimization.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $163000 - $236000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities- Create differentiated architectural innovations for Google's semiconductor Tensor Processing Unit (TPU) roadmap.
- Evaluate the power, performance, and cost of prospective architecture and subsystems.
- Collaborate with partners in Hardware Design, Software, Compiler, ML Model and Research teams for hardware/software co-design.
- Work on Machine Learning (ML) workload characterization and benchmarking.
- Develop architecture for differentiating features on next generation TPUs.
