Advanced Micro Devices, Inc

Integration RTL Design Engineer

Advanced Micro Devices, Inc$120K — $160K *
Telecommunications & Hardware
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
  • 5-7 years of experience in ASIC/SOC design roles.
  • Expert-level Verilog RTL coding skills.
  • Hands-on experience with complete ASIC design flow from RTL to tape-out.
  • Proficient in timing analysis and developing timing constraints.
  • Experience with complex ASIC IP integration into SOC designs.
  • Strong scripting skills in Python, Perl, Tcl, or Shell scripting.

Responsibilities

  • Author micro-architecture specifications and implement Verilog RTL for IP blocks.
  • Drive ASIC design from concept to production silicon, covering all phases.
  • Develop timing constraints and perform static timing analysis to achieve closure.
  • Integrate ASIC IP blocks into full-chip SOC environments, ensuring connectivity.
  • Ensure design quality through collaboration with verification teams and implement DFT.
  • Collaborate with physical design on floorplanning and timing convergence.
  • Automate tasks using scripting languages to enhance team productivity and design quality.
  • Engage with cross-functional teams to resolve technical challenges.

Benefits

  • Comprehensive health and wellness packages
  • Retirement savings plans
  • Employee stock purchase options
  • Flexible work arrangements
  • Professional development opportunities
Full Job Description
THE ROLE:

Join AMD's Silicon Design team to design and develop cutting-edge IPs for next-generation embedded products. As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design.

THE PERSON:

The ideal candidate is a seasoned ASIC/SOC designer with proven expertise across the entire chip development lifecycle-from RTL design through silicon bring-up. You excel in Verilog RTL coding, timing closure, and physical design awareness. With multiple production tape-outs under your belt, you bring deep technical expertise, strong ownership, and the ability to mentor junior engineers while driving projects to successful completion.

KEY RESPONSIBILITIES:
  • RTL Design & Microarchitecture: Author detailed micro-architecture specifications and own complete Verilog RTL implementation of major IP blocks, ensuring compliance with PPA (Performance, Power, Area) targets and timing requirements.
  • Full ASIC Development Lifecycle: Drive design from concept through production silicon across all phases: specification, RTL coding, lint/CDC checks, synthesis, timing analysis, verification, physical design integration, and post-silicon validation.
  • Timing Closure & Optimization: Develop and maintain timing constraints (SDC), perform static timing analysis (STA) using industry-standard tools (PrimeTime/Tempus), resolve timing violations, and collaborate with physical design to achieve timing closure.
  • SOC Integration: Integrate complex ASIC IP blocks into full-chip SOC environment, ensuring proper connectivity, clock domain crossings, and interface compliance with industry-standard protocols (AMBA AXI/AHB/APB, PCIe, CXL).
  • Design Quality & Verification: Partner with verification teams to ensure comprehensive functional coverage; implement design-for-test (DFT) and design-for-debug (DFD) features; participate in RTL quality reviews and signoff.
  • Physical Design Collaboration: Work closely with physical design engineers on floorplanning, placement constraints, clock tree synthesis, and power grid design to ensure timing convergence and manufacturing readiness.
  • Automation & Productivity: Develop Python/Perl/Tcl scripts to automate repetitive tasks, improve design quality checks, and enhance team efficiency throughout the design flow.
  • Cross-Functional Collaboration: Engage with architecture, verification, physical design, CAD, and post-silicon teams to resolve complex technical challenges and deliver high-quality silicon on schedule.


PREFERRED EXPERIENCE:
  • Proven track record with 2+ production ASIC tape-outs in senior design roles
  • Expert-level Verilog RTL coding skills with deep understanding of synthesizable RTL constructs and coding best practices
  • Hands-on experience with the complete ASIC design flow: RTL • Synthesis • STA • Physical Design • Tape-out
  • Experience writing and debugging SDC timing constraints, including multi-cycle paths, false paths, and clock domain crossing constraints
  • Experience integrating complex IP blocks into SOC designs
  • Knowledge of industry-standard on-chip interconnect protocols (AMBA AXI/AHB/APB)
  • Knowledge of ARM architecture and AMBA protocol specifications
  • Experience with low-power design techniques (clock gating, power gating, voltage scaling)
  • Proficiency in scripting languages: Python, Perl, Tcl, or Shell scripting
  • Exposure to formal verification tools for equivalence checking and property verification
  • Familiarity with AI-assisted design tools and modern EDA technologies
  • Experience mentoring junior engineers and leading design teams
  • Strong technical writing skills for design specifications and documentation
  • Excellent communication and collaboration skills in cross-functional environments

ACADEMIC QUALIFICATIONS:
  • Bachelor's or Master's degree in Electrical Engineering or Computer Engineering

LOCATION: San Jose, CA

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This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

About Advanced Micro Devices, Inc

Advanced Micro Devices, Inc. Careers

Join the innovative forefront of technology with a career at Advanced Micro Devices, Inc. (AMD), a leader in semiconductor development. As part of our global team, you will contribute to an organization renowned for its dedication to innovation, leadership, and diversity in the tech industry.

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Join a team of over 12,000 dedicated professionals at the intersection of technology, industry expertise, and digital innovation. At AMD, you will work on groundbreaking projects that shape the future of computing and graphics. Our collaborative environment encourages networking and the sharing of ideas across teams and disciplines.

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AMD is committed to the development of its employees. We offer robust training programs, including leadership development and diversity training, to ensure our team is equipped for both current challenges and future opportunities. Our benefits package is designed to support the well-being and financial security of our employees and their families.

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Learn more about Advanced Micro Devices, Inc
Size
15,500 employees
Market Cap
$100.9 billion
Industry
Net Income
$2.4 billion
Founded
1969
5 Year Trend
+30.9%
Revenue
$9.7 billion
NASDAQ

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