Advanced Micro Devices, Inc

High Speed IO Analog Mixed Signal Architect/ Design Engineer

Advanced Micro Devices, Inc$130K — $180K *
Telecommunications & Hardware
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • 5-7 years of hands-on experience in analog/mixed-signal IP design, particularly in high-speed interfaces and memory technologies.
  • Proven leadership experience with a track record in technical settings.
  • MS or PhD in Electrical or Computer Engineering or equivalent.
  • Strong communication and presentation abilities, capable of working across teams.
  • In-depth technical knowledge of mixed-signal design concepts and circuit architecture.

Responsibilities

  • Design and develop high-speed IO/DDR/die-to-die SerDes AMS circuit architectures.
  • Lead the definition, review, and sign-off processes for analog/mixed-signal IP top-level architecture.
  • Collaborate with system architects to translate system-level specifications into AMS blocks and circuit specifications.
  • Develop technical specifications and test plans for AMS blocks' pre-silicon verification and post-silicon characterizations.
  • Oversee layout pre-silicon, characterization, and debugging post-silicon validations.
  • Support product bring-up and sign-off on test plans and characterization reports.

Benefits

  • Comprehensive benefits package as outlined in AMD's benefits overview.
  • Opportunities for growth and professional development in cutting-edge technology.
  • Participation in hybrid work arrangements to promote work-life balance.
Full Job Description
THE ROLE:

Be part of AMD's analog/mixed signal IP design team responsible for the design and development of next generation IOs, high speed memory (LPDDRx, gDDRx, HBMx) and die-to-die Gbps proprietary PHY IP solutions. Establishes and maintains AMD's technological leadership position in analog circuit architecture and design with a proven track record for problem solving and innovation.

THE PERSON:

The ideal candidate has experience leading others in technical settings. You also have excellent communication, writing, and presentation skills.

KEY RESPONSIBLITIES:
  • High Speed IO/DDR/die-to-die (d2d)/SerDes AMS circuit architecture and design
  • Lead Definition, review and sign-off on analog/mixed signal IP top level architecture and component/circuit level specifications
  • Work and collaborate with System/Platform & SOC architects to translate system level specs to AMS blocks/circuit level specifications.
  • Author AMS blocks circuit and architecture technical specifications, AMS pre-silicon verification, AMS post-silicon characterization/validation test plans.
  • Supervise pre-silicon layout, post-silicon characterization and debug.
  • Support product bring-up and debug, and Sign-off on test-plans and characterization reports


PREFERRED EXPERIENCE:
  • Hand-on design experience in multi-Gbps serial interfaces (PCIE, USB, ...), parallel high BW memory interface PHY/IOs (LPDDRx, HBM, gDDR, ...) and die-to-die/chip-to-chip links PHY IPs
  • Strong fundamentals and knowledge of mixed signal circuit architecture and design techniques for receiver/transmitter and PLL/DLL/clocking. In-depth knowledge of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques
  • Solid experience of designing and architecting analog mixed-signal circuit blocks including DLLs, phase interpolator, low jitter clock distribution, bandgap, biasing circuits, LDO regulators, amplifiers, comparators. Experience in mixed signal design circuit blocks such as digital/analog DLLs, duty cycle corrector, clock and data recovery, clock mixer, ...
  • Solid Understanding of high-speed IO signaling topologies and architectures including system-silicon co-design/co-optimizations for best in class PPA.
  • Solid understanding of high speed IO link budget analysis and jitter/SNR metrics and design trades.
  • Experience in low power design techniques for high speed/custom digital circuit (e.g. CMOS/CML high speed design for counters, dividers, ...) design and analysis including transistor level timing sign-off
  • Solid understanding of power, area and performance trade-offs in mixed signal IP design
  • Design Experience in FinFet advanced CMOS process nodes 16nm/7nm/3nm and below coupled with a solid understanding of transistor device performance and fundamentals
  • Proficient in AMS design flows, tools, and methodologies. Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools
  • Work with project-manager, system architects, IC designers and physical designers to guarantee quality/timely deliverables meeting project's schedule and technical requirements
  • Analytical thinking, inventive, and Quality-oriented mindset. Strong and effective technical and management communication at the peer and upward management levels.
  • Track record of successfully taking AMS designs to production
  • Excellent written and verbal communication skills able to operate without direct supervision but also work cross-functionally, cross-geographies collaborating and being part of a multi-disciplinary team in a dynamic/fast-paced environment.
  • Exhibit strong initiative and ownership of tasks and responsibilities. Seek help proactively as well as share and pass on knowledge


ACADEMIC CREDENTIALS:
  • MS or PhD in Electrical, Computer Engineering or related equivalent


LOCATION: San Jose, anywhere in California

This role is not eligible for visa sponsorship.

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Benefits offered are described: AMD benefits at a glance.

About Advanced Micro Devices, Inc

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Learn more about Advanced Micro Devices, Inc
Size
15,500 employees
Market Cap
$100.9 billion
Industry
Net Income
$2.4 billion
Founded
1969
5 Year Trend
+30.9%
Revenue
$9.7 billion
NASDAQ

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