FPGA Development Tools Engineer - Placer

Altera Corporation

$110K — $120K *
Enterprise Technology
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's Degree in Computer Science, Computer Engineering, or related field
  • Proficient in C++ with hands-on experience
  • Familiarity with Verilog, Python, and TCL is advantageous

Responsibilities

  • Design and enhance FPGA placement algorithms to optimize performance
  • Contribute to the full FPGA compilation process with routing, synthesis, and timing teams
  • Enhance runtime performance and quality of results for complex designs
  • Develop timing-aware placement strategies for high-performance applications
  • Analyze placement quality and timing issues to optimize design closure
  • Integrate new algorithms into the compiler and validate across workflows

Benefits

  • Performance-based incentive opportunities
  • Access to diverse projects in a supportive team environment
  • Opportunity to impact crucial design technologies in the FPGA field
  • Flexible work arrangements and a focus on work-life balance
Full Job Description
Job Details:

Job Description:

This role focuses on developing and optimizing FPGA placement algorithms within the compiler toolchain, directly impacting performance, power efficiency, and overall design quality.

As part of the Quartus team, your responsibilities will include, but are not limited to:
  • Placement Algorithm Development:
    Design, implement, and enhance FPGA placement algorithms to optimize timing, congestion, and resource utilization.
  • Compiler Flow Enhancement:
    Contribute to the end-to-end FPGA compilation flow, working closely with routing, synthesis, and timing teams.
  • Performance Optimization:
    Improve runtime performance, scalability, and quality of results (QoR) for large and complex customer designs.
  • Timing-Driven Placement:
    Develop and refine timing-aware placement strategies to support high-frequency, performance-critical designs.
  • Debug & Analysis:
    Analyze placement quality, congestion hotspots, and timing bottlenecks; drive improvements to convergence and design closure.
  • Toolchain Integration:
    Integrate new placement capabilities into the compiler infrastructure and validate across diverse workloads.


Our compensation is designed to reflect the Canadian labour market. The actual salary offered may vary based on several factors, including the position's location, as well as the candidate's experience, skills, training, and job-specific knowledge. In addition to base salary, we offer performance-based incentive opportunities that reward both individual contributions and overall company success.

Estimated Salary Range: $110K- $120K CAD

We use artificial intelligence to screen, assess, or select applicants for the position. This posting is for an existing vacancy. Canadian work experience is not required for this role. Applicants must be eligible for any required Canada export authorizations.

Qualifications:
  • Bachelor's Degree in CS, Computer Engineering, or related field
  • Working experience with C++
  • Experience with Verilog, Python and TCL is a plus


Job Type:
Regular

Shift:
Shift 1 (Canada)

Primary Location:
Toronto, Ontario, Canada

Additional Locations:

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