THE ROLE
We are seeking a Fellow Architect to define and drive next-generation architecture for AMD's adaptive FPGA devices. This role will own the architecture for FPGA configuration, readback, and Partial Reconfiguration (PR), enabling scalable, secure, and flexible deployment of programmable logic in heterogeneous SoC and chiplet environments.
As a senior technical leader, you will shape the long-term vision for bitstream architecture, configuration flows, runtime reconfiguration, debug observability, and system integration, translating customer requirements across Emulation & Prototyping, AI, Data Center, Embedded, and Automotive into differentiated FPGA capabilities. You will collaborate across silicon, RTL, tools, software, and customer teams.
THE PERSON
You are a recognized expert in FPGA architecture with deep expertise of Configuration and Partial Reconfiguration. You have strong understanding of configuration architecture including bitstream, protocols, boot flows, security, readback and debug. You have deep appreciation of trade-offs across reliability, performance, power, and robustness. You are proven advocate and practitioner of Partial Reconfiguration at system scale. You have experience in ASIC/SoC design, enabling effective integration with hardened subsystems and modern interconnects.
You bring clarity to complex problems and influence technical direction across organizations.
KEY RESPONSIBILITIES
- Own FPGA configuration architecture, including bitstream, boot flows, interfaces, compression, security, and reliability
- Define next-generation Partial Reconfiguration architecture for low-latency, secure dynamic updates
- Drive innovation in runtime reconfiguration for high-availability and adaptive systems
- Architect readback, debug, and observability infrastructure for validation and in-field diagnostics
- Define configuration security, including secure boot, key management, and update flows
- Drive system trade-offs across configuration bandwidth, latency, and power, including memory and interconnect interactions
- Develop clear architecture specifications for configuration, PR, and debug subsystems
- Align with software/tools teams for end-to-end configuration and PR flows
- Collaborate with silicon and design teams for scalable high-quality implementation
- Influence product roadmap and customer engagement for PR-driven solutions
- Mentor architects and elevate FPGA architecture standards across the organization
PREFERRED EXPERIENCE
- Strong Expertise in FPGA configuration, Partial Reconfiguration, and bitstream architecture
- Experience with readback/debug infrastructure and field diagnostics
- Background in ASIC/SoC design flows
- Familiarity with FPGA toolchains (synthesis, P&R, PR flows)
- Ability to define architecture across silicon, tools, and software layers
ACADEMIC CREDENTIALS
- BS, MS, or PhD in Electrical/Computer Engineering or related field
- Recognized technical leader in FPGA systems or architecture with significant architectural contributions, patents, publications, or industry impact
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Benefits offered are described: AMD benefits at a glance.
