Job Details:Job Description:The Role and ImpactJoin Intel's mission to engineer world-changing technology as an EDA Tools Hardware Engineer. We are seeking an experienced EDA CAD / Tool Flow Development Engineer to develop and maintain transistor-level timing characterization flows for custom IPs, embedded memories, SRAMs, register files, and compiler-generated macros across advanced semiconductor technologies.
This role focuses on characterization methodology, CAD infrastructure, automation, and model validation for complex custom macros and memory IPs. The engineer will work closely with custom circuit, memory design, STA, and methodology teams to enable scalable and silicon-accurate timing, power, and noise modeling flows.
The ideal candidate has strong expertise in SPICE-based characterization, Liberty model generation, custom macro timing behavior, and large-scale automation using industry-standard tools such as Synopsys NanoTime and Cadence Liberate.
Key Responsibilities - Develop, test, and analyze engineering design automation tools, flows, and methodologies to improve efficiency and optimize power and performance.
- Collaborate with EDA vendors to define, evaluate, and test next-generation design tools and flows.
- Create and verify unique hardware designs, integrating components into hierarchical systems to support end-to-end EDA tool testing for advanced technology nodes.
- Define and enable methodologies for hardware development related to EDA tools and technology node advancements.
- Support and enhance platforms, databases, scripts, and tools used for design automation.
- Provide digital design, verification, full-chip integration, physical layout, power, performance, clocking, and timing for future TFM development.
Qualifications:Minimum Qualifications- Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field and 6+ years of relevant experience; OR
- Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field and 4+ years of relevant experience; OR
- PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field and 2+ years of relevant experience.
- Timing characterization methodologies in one of the following: (i.e. Nanotime, Liberate, PrimeLib)
- Experience with Liberty timing models
Preferred Qualifications Experience in any of the following:- SPICE simulation
- CMOS circuits
- Memory architecture fundamentals
- STA fundamentals
- Advanced-node custom IP or memory characterization flows
- Scripting and automation skills in Linux environments
Job Type:Experienced Hire
Shift:Shift 1 (United States of America)
Primary Location:US, California, Santa Clara
Additional Locations:US, California, Folsom, US, Oregon, Hillsboro, US, Texas, Austin
Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
