DV Formal Verification

DensityAI

$200K — $420K *
Consumer Technology
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • Exceptional abilities in formal verification including property authoring and proof strategies.
  • Master's degree plus 8 years of experience in block- and full-chip formal verification on complex SOCs.
  • Proven track record in debugging proof failures and driving convergence with RTL designers.
  • Hands-on experience with industry-standard formal tools like Synopsys VC Formal or Cadence Jasper.
  • (Optional) Familiarity with security verification, processor verification, and AMS/IP flow.

Responsibilities

  • Own block- and SOC-level formal verification for AI accelerator silicon.
  • Debug and manage proof convergence for complex designs.
  • Develop AI-assisted tool flows for enhanced verification processes.
  • Collaborate with chip-design and software teams throughout the AI accelerator program.
  • Drive initiatives from initial silicon development to scaling.

Benefits

  • Equity grant opportunity based on company guidelines.
  • Comprehensive medical, dental, and vision coverage.
  • 401(k) retirement plan available.
  • Standard paid time off (PTO) program.
  • Visa sponsorship and immigration support provided.
Full Job Description
ITAR Notice: This role involves access to ITAR-controlled information. Applicants must be U.S. persons (U.S. citizens, U.S. permanent residents, asylees, or refugees) per 22 CFR 120.62.
About the role

Own block- and SOC-level formal verification, debug, and proof convergence for our AI accelerator silicon. Work with chip-design and software teams driving DensityAI's AI accelerator program from first silicon through scale-out.
What you'll do
  • Own block- and SOC-level formal verification, debug, and proof convergence for our AI accelerator silicon
  • Use and develop AI-assisted tool flows - including AI agents for proof guidance - to accelerate convergence on complex designs
What we're looking for
  • Exceptional abilities in formal verification: property authoring (SVA / PSL), proof strategies, and tool-flow ownership
  • Master's + 8 years of experience in block- and full-chip formal verification on complex SOCs
  • Demonstrated ability to debug proof failures and drive convergence in collaboration with RTL designers and architects
  • Hands-on with industry-standard formal tools (Synopsys VC Formal, Cadence Jasper, or equivalent)
  • (Optional) Security verification, processor verification, equivalence checking, or AMS / IP-flow exposure
Compensation

Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.
Visa Sponsorship

DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.
Export Controls

Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.

Full compensation packages are based on candidate experience and relevant certifications.

California pay range

$200,000-$420,000 USD

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