Job DescriptionIn this position, you will be working on Architecting and Designing high-speed mixed-signal SerDes circuits using state-of-the art process technology, as well as be involved in the design of high-performance digital circuits interfacing to leading edge analog circuitry as part of an overall system. You will be working on multiple Audio-Video protocols including DisplayPort, MIPI CSI over CPHY/DPHY enabling solutions that require handling multiple AV streams, video processing, stream encryption and compression.
Your responsibilities will include defining architecture and micro-architecture, RTL coding, simulation, synthesis, timing closure, verification, evaluation, debugging of high-speed SerDes chips both at the circuit level and behavioral level.
As a design engineer, you will prepare test methods and specifications, assist in preparation of application information, data sheets and demo boards. You will develop solutions to complex problems through assessment of various techniques and approaches. You will plan and organize work to ensure timely completion of many independent tasks with general instructions on routine tasks and with detailed instructions on new assignments.
This position involves routine communication with a highly talented team of analog and digital design engineers to solve problems and present information as well as active participation in work groups, providing ideas and collaborative teamwork.
QualificationsMinimum requirements:- BSEE with 12 years or MSEE with 10 years of digital/mixed signal ASIC architecture/design experience
- Successfully taped out multiple devices
- A thorough understanding of digital logic design
- Strong understanding of ASIC design flow from RTL to GDSII.
- Familiarity with the Verilog language and simulators
- A good understanding of analog functionality and exposure to analog IC design methods
- Ability to solve problems using a systematic approach
Preferred qualifications:- RTL coding and synchronous/asynchronous digital skills
- Experience with SystemVerilog
- Knowledge of simulation tools like Xcelium, code coverage and debug tools
- Knowledge of PLL, SerDes, Encoders, Decoders, Video Compression, MIPI Standards, Video Encryption, DisplayPort, I2C and SPI
- Synthesis, STA, Lint checkers, Clock domain crossing (CDC) checkers, Logic equivalence checking.
- Scripting skills in Perl, Tcl, Python etc.
- Demonstrated strong analytical and problem-solving skills
- Strong verbal and written communication skills
- Ability to work in teams and collaborate effectively with people in different functions
- Strong time management skills that enable on-time project delivery
- Ability to work effectively in a fast-paced and rapidly changing environment
- Ability to take the initiative and drive for results
- Demonstrated ability to build strong, influential relationships
- Good listener and excellent verbal and written communication skills
Additional Preferred Experience/Skills- Familiarity with low power design techniques
- Knowledge of DisplayPort including HDCP and DSC, MIPI CPHY/DPHY
- Knowledge of UVM, SystemVerilog, constrained random and assertion-based verification methodologies
- Knowledge or experience of FPGA prototyping and Palladium
- Knowledge of MATLAB
- Knowledge or experience with physical design flow
- Strong time management skills that enable on-time project delivery
About the TeamTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.
